Abstract: A PMOS device less affected by negative bias time instability (NBTI) and a method for forming the same are provided. The PMOS device includes a barrier layer over at least a portion of a gate structure, a gate spacer, and source/drain regions of a PMOS device. A stressed layer is then formed over the barrier layer. The barrier layer is preferably an oxide layer and is preferably not formed for NMOS devices.

Abstract: A PMOS device less affected by negative bias time instability (NBTI) and a method for forming the same are provided. The PMOS device includes a barrier layer over at least a portion of a gate structure, a gate spacer, and source/drain regions of a PMOS device. A stressed layer is then formed over the barrier layer. The barrier layer is preferably an oxide layer and is preferably not formed for NMOS devices.

Abstract: A process is described for forming a buried, or pocket, ion implant in a semiconductor device. In particular, said pocket is limited to only the drain side of a field effect transistor. To achieve this the photoresist that is used to protect the source and drain regions during ion implantation is located at different distances from the gate pedestal. The photoresist on the source side is placed closer to the gate pedestal than it is on the drain side. As a result, when ions arrive at the surface at a sufficiently shallow angle to be able to penetrate the semiconductor regions immediately beneath the gate oxide, photoresist at the source side blocks the beam while the photoresist on the drain side is far enough away from the gate not to intercept the beam. Thus, a single asymmetrically located pocket is formed in a single step.

Abstract: The present invention is a method of protecting an alignment mark in semiconductor manufacturing process with CMP. This invention utilizes a via mask or masking blade to remove the intermetal dielectric layer on a wide clear -out window using two etching steps. One etching step is performed before intermetal dielectric layer polish. The other etching step is performed after intermetal dielectric layer polish. Thus, there is no intermetal dielectric layer remained on the alignment mark and the alignment mark keeps the original shape.

Abstract: A method is described for forming a high contact resistance region within the drain region or source region of an insulated gate field effect transistor as part of a high resistance resistor for electrostatic discharge protection of the field effect transistor. The silicide free contact region is formed as part of a self aligned silicide, or salicide, contact process. Nitrogen ion implantation followed by annealing is used to form a silicon nitride mask at the silicide free contact region. The mask prevents the formation of low contact resistance metal silicide at the silicide free contact region during the salicide process. Low resistance contacts to the gate electrode, source, and drain are formed using metal silicide.

Abstract: A method is described for forming a high contact resistance region within the drain region or source region of an insulated gate field effect transistor as part of a high resistance resistor for electrostatic discharge protection of the field effect transistor. The high resistance contact region is formed as part of a self aligned silicide, or salicide, contact process. Nitrogen ion implantation at the high resistance contact region into the metal which will be used to form the metal silicide low resistance contacts converts the metal at the high resistance contact region to metal nitride. Since all the metal at the high resistance contact region is converted to metal nitride there is no free metal to form metal silicide at the high resistance contact region when the low resistance metal silicide contacts are formed. Low resistance contacts to the gate electrode, source, and drain are formed using metal silicide.

Abstract: A salicide process for manufacturing a lightly doped drain (LDD) MOS transistor having unshorted titanium silicide gate electrode and source/drain contacts. The salicide method comprises forming a titanium (Ti) layer on the surface of the substrate, the sidewall spacers and the gate electrode. Nitrogen is implanted at a large angle into the Ti layer, especially over the sidewall spacers, thus converting all the titanium layer over the spacers to titanium nitride. Next, the titanium layer is thermally annealed forming titanium silicide on the top surface of the gate electrode and in the highly doped source/drain regions. The titanium nitride layer and any of the remaining titanium layer is etched away thereby leaving unshorted titanium silicide on the top surface of the gate electrode and in the highly doped source/drain regions. The TiN layer over the sidewall spacers prevents a titanium silicide bridge from forming between/he gate electrode and the source/drain regions during the thermal anneal process.