Abstract: A manufacturing process for a thermally enhanced package is disclosed. First, a substrate strip including at least a substrate is provided. Next, at least a chip is disposed on an upper surface of the substrate, and the chip is electrically connected to the substrate. Then, a prepreg and a heat dissipating metal layer are provided, and the heat dissipating metal layer is disposed on a first surface of the prepreg and a second surface of the prepreg faces toward the chip. Finally, the prepreg covers the chip by laminating the prepreg and the substrate.

Abstract: A flip chip package process is provided. First, a substrate strip including at least one substrate is provided. Next, at least one chip is disposed on the substrate, and the chip is electrically connected to the substrate. Then, a stencil having at least one opening and an air slot hole is disposed on an upper surface of the substrate strip, an air gap is formed between the stencil and the substrate strip, the air gap connects the opening and the air slot hole, and the chip is located in the opening. Finally, a liquid compound is formed into the opening of the stencil to encapsulate the chip, and a vacuum process is performed through the air slot hole and the air gap, so as to prevent the air inside the opening from being encapsulated by the liquid compound to become voids.

Abstract: A flip-chip package structure with stiffener includes a substrate, a first stiffener positioned on a surface of the substrate, a chip having a plurality of bumps adopted to electrically connect the substrate and the chip, and a second stiffener positioned on the surface of the substrate and connected with the first stiffener. The first stiffener is positioned outside of the second stiffener.

Abstract: A flip chip package process is provided. First, a substrate strip including at least one substrate is provided. Next, at least one chip is disposed on the substrate, and the chip is electrically connected to the substrate. Then, a stencil having at least one opening and an air slot hole is disposed on an upper surface of the substrate strip, an air gap is formed between the stencil and the substrate strip, the air gap connects the opening and the air slot hole, and the chip is located in the opening. Finally, a liquid compound is formed into the opening of the stencil to encapsulate the chip, and a vacuum process is performed through the air slot hole and the air gap, so as to prevent the air inside the opening from being encapsulated by the liquid compound to become voids.

Abstract: A manufacturing process for a thermally enhanced package is disclosed. First, a substrate strip including at least a substrate is provided. Next, at least a chip is disposed on an upper surface of the substrate, and the chip is electrically connected to the substrate. Then, a prepreg and a heat dissipating metal layer are provided, and the heat dissipating metal layer is disposed on a first surface of the prepreg and a second surface of the prepreg faces toward the chip. Finally, the prepreg covers the chip by laminating the prepreg and the substrate.

Abstract: A method of fabricating a semiconductor package having electromagnetic interference shielding starts with providing a substrate and a semiconductor device. Subsequently, a molding compound is provided. The molding compound covers the semiconductor device, and contacts with parts of the substrate. Next, a conductive adhesive layer is formed on the surface of the molding compound, and directly covers the top surface and the side surface of the molding compound. Because the conductive adhesive layer is utilized as an electromagnetic interference shielding, the fabricating process of the electromagnetic interference shielding is extremely simplified.

Abstract: A flip-chip package structure with stiffener includes a substrate, a first stiffener positioned on a surface of the substrate, a chip having a plurality of bumps adopted to electrically connect the substrate and the chip, and a second stiffener positioned on the surface of the substrate and connected with the first stiffener. The first stiffener is positioned outside of the second stiffener.

Abstract: A wafer-level package structure, applicable to a flip-chip arrangement on a carrier, which comprises a plurality of contact points, is described. This wafer-level package structure is mainly formed with a chip and a conductive layer. The conductive layer is arranged on the bonding pads of the chip as contact points. The conductive layer can further be arranged at a region outside the bonding pads on the chip as a heat sink to enhance the heat dissipation ability of the package.

Abstract: A process of fabricating flip-chip packages is disclosed. First, a substrate having a carrying surface is provided. Next, a chip is provided, wherein the chip has an active surface, a plurality of bonding pads are disposed on the active surface and on each bonding pad a bump is disposed. Afterwards, the active surface of the chip is placed to face the carrying surface of the substrate, so that the chip is electrically connected to the substrate via the bumps and a flip-chip package is formed. Further, an underfill is filled between the substrate and the chip to encapsulates the bumps, while the processing temperature is kept between 100° C. and 140° C. for the underfill to be partially cured. Furthermore, the underfill is heated to be fully cured. By means of the process of fabricating flip-chip packages, the material uniformity after curing the underfill is solidly improved.

Abstract: A method of forming bumps on the active surface of a silicon wafer. A first under-bump metallic layer is formed over the active surface of the wafer. A second under-bump metallic layer is formed over the first under-bump metallic layer. A portion of the second under-bump metallic layer is removed to expose the first under-bump metallic layer. A plurality of solder bumps is implanted onto the second under-bump metallic layer. The exposed first under-bump metallic layer is removed so that only the first under-bump metallic layer underneath the second under-bump metallic layer remains.

Abstract: A bump fabrication process for forming a bump over a wafer having a plurality of bonding pads thereon is provided. A patterned solder mask layer having a plurality of openings that exposes the respective bonding pads is formed over a wafer. The area of the opening in a the cross-sectional area through a the bottom-section as well as through a the top-section of the opening is smaller than the area of the opening in a the cross-sectional area through a the mid-section of the opening. Solder material is deposited into the opening and then a reflow process is conducted fusing the solder material together to form a spherical bump inside the opening. Finally, the solder mask layer is removed. In addition, a pre-formed bump may form on the bonding pad of the wafer prior to forming the patterned solder mask layer over the wafer having at least with an opening that exposes the pre-formed bump.

Abstract: A bumping process, which is a method of forming a plurality of bumps over a wafer, is provided. The wafer has an active surface having a passivation layer and a plurality of bonding pads thereon. The passivation layer exposes the bonding pads on the active surface. An adhesion layer is formed over the active surface of the wafer covering both the bonding pads and the passivation layer. A metallic layer is formed over the adhesion layer. The adhesion layer and the metallic layer are patterned, so that the adhesion layer and the metallic layer remain on top of the bonding pads. A photoresist layer is formed on the active surface of the wafer. The photoresist layer has a plurality of openings that exposes the metallic layer. Next, solder balls with a solidified material on the surface of each solder ball are disposed into each opening. Then, a reflow process is carried out, so that the solder balls bond with the metallic layer. Finally, the photoresist layer is removed.

Abstract: A semiconductor device with a capability can prevent a burnt fuse pad from re-electrical connection, wherein the semiconductor device includes a bump pad and a fuse pad over a wafer. The fuse pad includes the burnt fuse pad having a gap for electrical isolation. The semiconductor device comprises a dielectric layer, disposed substantially above the burnt fuse pad and filling the gap, and a bump structure, disposed on the bump pad. The foregoing semiconductor device can further comprise a passivation layer, which exposes the bump pad and a portion of the burnt fuse pad. Wherein, the dielectric layer is over the passivation layer, covers the exposed portion of the burnt fuse pad and fills the gap.

Abstract: A bumping process, which is a method of forming a plurality of bumps over a wafer, is provided. The wafer has an active surface having a passivation layer and a plurality of bonding pads thereon. The passivation layer exposes the bonding pads on the active surface. An adhesion layer is formed over the active surface of the wafer covering both the bonding pads and the passivation layer. A metallic layer is formed over the adhesion layer. The adhesion layer and the metallic layer are patterned so that the adhesion layer and the metallic layer remain on top of the bonding pads. A photoresist layer is formed on the active surface of the wafer. The photoresist layer has a plurality of openings that exposes the metallic layer. Next, solder balls are disposed into each opening and melted partially to bond to the metallic layer temporarily by performing a heating process simultaneously. Then, a process of disposing the flux material in the openings to cover the surfaces of the solder balls is performed.

Abstract: A method of modifying the tin to lead ratio of a tin-lead bump forms a patterned solder mask over a substrate that comprises a first tin-lead bump formed thereon, the patterned solder mask having an opening that exposes the tin-lead bump. A solder material including tin and lead is filled in the opening of the solder mask over the first tin-lead bump. The solder material has a tin to lead ratio that differs from that of the first tin-lead bump. The solder material is reflowed to fuse with the first tin-lead bump, which forms a second tin-lead bump. The tin to lead ratio of the second tin-lead bump is thereby different from that of the first tin-lead bump.

Abstract: A method of forming a bump on an active surface of a wafer is disclosed. The method of the invention forms an under ball metallurgy (UBM) onto the active surface of the wafer. Then, the UBM is partially removed until a portion of the active surface of the wafer is exposed. At least one conductive stud is bonded onto the non-removed UBM by wire bonding.

Abstract: A solder ball fabricating process for forming solder balls over a wafer having an active layer is provided. A patterned solder mask layer is formed over the active surface of the wafer. The patterned solder mask layer has an opening that exposes a bonding pad on the wafer. Solder material is deposited into the opening over the bonding pad. A reflow process is conducted to form a pre-solder body. The aforementioned steps are repeated so that various solder materials are fused together to form a solder ball over the bonding pad.

Abstract: A wafer bump fabrication process is provided in the present invention. A wafer with multiple bonding pads and a passivation layer, which exposes the bonding pads, is provided. The surface of each bonding pad has an under bump metallurgy layer. A patterned photoresist layer with a plurality of opening is formed which openings expose the under bump metallurgy layer. Afterwards a curing process is performed to cure the patterned photoresist layer. Following a solder paste fill-in process is performed to fill a solder paste into the openings. A reflow process is performed to form bumps from the solder paste in the openings. The patterned photoresist layer is removed.

Abstract: A method of forming bumps on the active surface of a silicon wafer. An under-ball metallic layer is formed over the active surface of the wafer. A plurality of first solder blocks is attached to the upper surface of the under-ball metallic layer. Each first solder block has an upper surface and a lower surface. The lower surface of each first solder block bonds with the under-ball metallic layer. The upper surfaces of the first solder blocks are planarized. A second solder block is attached to the upper surface of each first solder block and then a reflow operation is carried out.

Abstract: A bumping process, which is a method of forming a plurality of bumps over a wafer, is provided. The wafer has an active surface having a passivation layer and a plurality of bonding pads thereon. The passivation layer exposes the bonding pads on the active surface. An adhesion layer is formed over the active surface of the wafer covering both the bonding pads and the passivation layer. A metallic layer is formed over the adhesion layer. The adhesion layer and the metallic layer are patterned, so that the adhesion layer and the metallic layer remain on top of the bonding pads. A photoresist layer is formed on the active surface of the wafer. The photoresist layer has a plurality of openings that exposes the metallic layer. Next, solder balls with a solidified material on the surface of each solder ball are disposed into each opening. Then, a reflow process is carried out, so that the solder balls bond with the metallic layer. Finally, the photoresist layer is removed.