Patents by Inventor Jau Wu

Jau Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200027003
    Abstract: A packaging methodology for radioactive dismantled parts of nuclear facilities is provided. This methodology integrates voxelization and metaheuristic to discretize the irregular 3D shape of various dismantled parts and put them into the containers with greatest efficiency. To enumerate the possible locations and orientations of an irregular part effectively, the solid models of the dismantled parts are descripted to user-specified voxelization operations. Therefore, discretized parts and container yield a finite space of optimal solutions and make the evolution algorithm viable for optimization quest. This methodology improves the package efficiency of the radioactive dismantled parts to reduce the required quantity of the storage containers.
    Type: Application
    Filed: April 25, 2019
    Publication date: January 23, 2020
    Inventors: HUANG-JAU WU, CHUNG-HAO HUANG, FENG-CHENG YANG
  • Patent number: 10436840
    Abstract: A distributed test circuit includes partitions arranged in series to form a scan path, each partition including a scan multiplexer, a test data register, and a segment insertion bit component. The scan multiplexer of each partition provides inputs to the corresponding test data register of the each partition. Broadcast control logic generates a select signal to the scan multiplexer of each partition to place the test circuit in a broadcast mode when the select signal is asserted, and to switch the test circuit to a daisy mode when select signal is de-asserted. The segment insertion bit is operable to include or bypass each partition from the scan path.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: October 8, 2019
    Assignee: NVIDIA Corp.
    Inventors: Jau Wu, Saurabh Gupta
  • Publication number: 20190128963
    Abstract: A distributed test circuit includes partitions arranged in series to form a scan path, each partition including a scan multiplexer, a test data register, and a segment insertion bit component. The scan multiplexer of each partition provides inputs to the corresponding test data register of the each partition. Broadcast control logic generates a select signal to the scan multiplexer of each partition to place the test circuit in a broadcast mode when the select signal is asserted, and to switch the test circuit to a daisy mode when select signal is de-asserted. The segment insertion bit is operable to include or bypass each partition from the scan path.
    Type: Application
    Filed: March 26, 2018
    Publication date: May 2, 2019
    Inventors: Jau Wu, Saurabh Gupta