Patents by Inventor Jaume Abella
Jaume Abella has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10528473Abstract: Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.Type: GrantFiled: June 13, 2017Date of Patent: January 7, 2020Assignee: Intel CorporationInventors: Christopher Wilkerson, Muhammad M. Khellah, Vivek De, Ming Zhang, Jaume Abella, Javier Carretero Casado, Pedro Chaparro Monferrer, Xavier Vera, Antonio Gonzalez
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Patent number: 10020037Abstract: An apparatus for storing X-bit digitized data, the register file comprising: a plurality of registers each register configured for storing X bits, wherein each register is partitioned into Y sub-registers such that each sub-register stores at least X/Y bits, and wherein at least one extra X/Y-bit sub-register is incorporated in each register to provide redundancy in the number of sub-registers for a total of at least Y+1 sub-registers per register, so that if a first sub-register in a first register includes faulty bits, data destined for storage in the first sub-register is stored in a second sub-register, in the first register, that does not include faulty bits.Type: GrantFiled: December 10, 2007Date of Patent: July 10, 2018Assignee: Intel CorporationInventors: Jaume Abella, Javier Carretero Casado, Pedro Chaparro Monferrer, Xavier Vera
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Publication number: 20180060239Abstract: Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.Type: ApplicationFiled: June 13, 2017Publication date: March 1, 2018Inventors: CHRISTOPHER WILKERSON, MUHAMMAD M. KHELLAH, VIVEK DE, MING ZHANG, JAUME ABELLA, JAVIER CARRETERO CASADO, PEDRO CHAPARRO MONFERRER, XAVIER VERA, ANTONIO GONZALEZ
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Patent number: 9678878Abstract: Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.Type: GrantFiled: October 16, 2012Date of Patent: June 13, 2017Assignee: Intel CorporationInventors: Christopher Wilkerson, Muhammad M. Khellah, Vivek De, Ming Zhang, Jaume Abella, Javier Carretero Casado, Pedro Chaparro Monferrer, Xavier Vera, Antonio Gonzalez
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Publication number: 20140108733Abstract: Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.Type: ApplicationFiled: October 16, 2012Publication date: April 17, 2014Inventors: Christopher Wilkerson, Muhammad M. Khellah, Vivek De, Ming Zhang, Jaume Abella, Javier Carretero Casado, Pedro Chaparro Monferrer, Xavier Vera, Antonio Gonzalez
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Patent number: 8578137Abstract: Methods and apparatus to reduce aging effect on registers are described. In one embodiment, a select value is stored in a register that is unused, for example, to reduce the effects of negative bias temperature instability (NBTI) or oxide degradation on the register. Other embodiments are also described.Type: GrantFiled: November 3, 2006Date of Patent: November 5, 2013Assignee: Intel CorporationInventors: Jaume Abella, Xavier Vera, Antonio Gonzalez
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Patent number: 8477558Abstract: Low supply voltage memory apparatuses are presented. In one embodiment, a memory apparatus comprises a memory and a memory controller. The memory controller includes a read controller. The read controller prevents a read operation to a memory location from being completed, for at least N clock cycles after a write operation to the memory location, where N is the number of clock cycles for the memory location to stabilize after the write operation.Type: GrantFiled: October 30, 2008Date of Patent: July 2, 2013Assignee: Intel CorporationInventors: Jaume Abella, Xavier Vera, Javier Carretero Casado, Pedro Chaparro Monferrer, Antonio González
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Patent number: 8402310Abstract: In one embodiment, the present invention includes a method for determining a vulnerability level for an instruction executed in a processor, and re-executing the instruction if the vulnerability level is above a threshold. The vulnerability level may correspond to a soft error likelihood for the instruction while the instruction is in the processor. Other embodiments are described and claimed.Type: GrantFiled: October 28, 2011Date of Patent: March 19, 2013Assignee: Intel CorporationInventors: Xavier Vera, Oguz Ergin, Osman Unsal, Jaume Abella, Antonio González
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Patent number: 8352812Abstract: Embodiments of apparatuses and methods for protecting data storage structures from intermittent errors are disclosed. In one embodiment, an apparatus includes a plurality of data storage locations, execution logic, error detection logic, and control logic. The execution logic is to execute an instruction to generate a data value to store in one of the data storage locations. The error detection logic is to detect an error in the data value stored in the data storage location. The control logic is to respond to the detection of the error by causing the execution logic to re-execute the instruction to regenerate the data value to store in the data storage location, causing the error detection logic to check the data value read from the data storage location, and deactivating the data storage location if another error is detected.Type: GrantFiled: August 3, 2007Date of Patent: January 8, 2013Assignee: Intel CorporationInventors: Xavier Vera, Jaume Abella, Javier Carretero Casado, Antonio González
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Patent number: 8291168Abstract: Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.Type: GrantFiled: December 31, 2011Date of Patent: October 16, 2012Assignee: Intel CorporationInventors: Christopher Wilkerson, Muhammad M. Khellah, Vivek De, Ming Zhang, Jaume Abella, Javier Carretero Casado, Pedro Chaparro Monferrer, Xavier Vera, Antonio Gonzalez
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Publication number: 20120110266Abstract: Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.Type: ApplicationFiled: December 31, 2011Publication date: May 3, 2012Inventors: Christopher Wilkerson, M. Muhammad Khellah, Vivek De, Ming Y. Zhang, Jaume Abella, Javier Carretero Casado, Pedro Chaparro Monferrer, Xavier Vera, Antonio Gonzalez
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Patent number: 8151094Abstract: The present invention includes a method for obtaining dynamic operating parameter information of a semiconductor device such as a processor, determining dynamic usage of the device, either as a whole or for one or more portions thereof, based on the dynamic operating parameter information, and dynamically estimating a remaining lifetime of the device based on the dynamic usage. Depending on the estimated remaining lifetime, the device may be controlled in a desired manner.Type: GrantFiled: December 30, 2005Date of Patent: April 3, 2012Assignee: Intel CorporationInventors: Xavier Vera, Jaume Abella, Osman Unsal, Oguz Ergin, Antonio González
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Publication number: 20120047398Abstract: In one embodiment, the present invention includes a method for determining a vulnerability level for an instruction executed in a processor, and re-executing the instruction if the vulnerability level is above a threshold. The vulnerability level may correspond to a soft error likelihood for the instruction while the instruction is in the processor. Other embodiments are described and claimed.Type: ApplicationFiled: October 28, 2011Publication date: February 23, 2012Inventors: Xavier Vera, Oguz Ergin, Osman Unsal, Jaume Abella, Antonio González
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Patent number: 8103830Abstract: Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.Type: GrantFiled: September 30, 2008Date of Patent: January 24, 2012Assignee: Intel CorporationInventors: Christopher Wilkerson, Muhammad M. Khellah, Vivek De, Ming Zhang, Jaume Abella, Javier Carretero Casado, Pedro Chaparro Monferrer, Xavier Vera, Antonio Gonzalez
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Patent number: 8090996Abstract: In one embodiment, the present invention includes a method for determining a vulnerability level for an instruction executed in a processor, and re-executing the instruction if the vulnerability level is above a threshold. The vulnerability level may correspond to a soft error likelihood for the instruction while the instruction is in the processor. Other embodiments are described and claimed.Type: GrantFiled: March 31, 2006Date of Patent: January 3, 2012Assignee: Intel CorporationInventors: Xavier Vera, Oguz Ergin, Osman Unsal, Jaume Abella, Antonio González
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Patent number: 8074110Abstract: In one embodiment, the present invention includes a method for identifying available cores of a many-core processor, allocating a first subset of the cores to an enabled state and a second subset of the cores to a spare state, and storing information regarding the allocation in a storage. The allocation of cores to the enables state may be based on a temperature-aware algorithm, in certain embodiments. Other embodiments are described and claimed.Type: GrantFiled: February 28, 2006Date of Patent: December 6, 2011Assignee: Intel CorporationInventors: Xavier Vera, Osman Unsal, Oguz Ergin, Jaume Abella, Antonio González
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Patent number: 8069376Abstract: Methods and apparatuses for on-line testing for decode logic are presented. In one embodiment, a processor comprises translation logic to decode an instruction to micro-operations and extraction logic to determine first information about numbers of occurrences of fields in the micro-operations. In one embodiment, the processor further comprises verification logic to indicate whether the decoding results of the instruction are accurate based at least on the first information.Type: GrantFiled: May 20, 2009Date of Patent: November 29, 2011Assignee: Intel CorporationInventors: Pedro Chaparro Monferrer, Jaume Abella, Xavier Vera, Javier Carretero Casado
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Patent number: 7895415Abstract: Apparatus and computing systems associated with cache sharing based thread control are described. One embodiment includes a memory to store a thread control instruction and a processor to execute the thread control instruction. The processor is coupled to the memory. The processor includes a first unit to dynamically determine a cache sharing behavior between threads in a multi-threaded computing system and a second unit to dynamically control the composition of a set of threads in the multi-threaded computing system. The composition of the set of threads is based, at least in part, on thread affinity as exhibited by cache-sharing behavior. The thread control instruction controls the operation of the first unit and the second unit.Type: GrantFiled: February 14, 2007Date of Patent: February 22, 2011Assignee: Intel CorporationInventors: Antonio Gonzalez, Josep M. Codina, Pedro Lopez, Fernando Latorre, Jose-Alejandro Pineiro, Enric Gibert, Jaume Abella, Jaideep Moses, Donald Newell, Ravishankar Iyer, Ramesh G. Illikkal, Srihari Makineni
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Publication number: 20100299507Abstract: Methods and apparatuses for on-line testing for decode logic are presented. In one embodiment, a processor comprises translation logic to decode an instruction to micro-operations and extraction logic to determine first information about numbers of occurrences of fields in the micro-operations. In one embodiment, the processor further comprises verification logic to indicate whether the decoding results of the instruction are accurate based at least on the first information.Type: ApplicationFiled: May 20, 2009Publication date: November 25, 2010Inventors: Pedro Chaparro Monferrer, Jaume Abella, Xavier Vera, Javier Carretero Casado
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Patent number: 7747913Abstract: Embodiments of apparatuses and methods for correcting intermittent errors in data storage structures are disclosed. In one embodiment, an apparatus includes a data storage location, error detection logic, inverting logic, control logic, operating logic, and evaluation logic. The error detection logic is to detect an error in a data value read from the data storage location. The inverting logic is to invert the erroneous data value to produce an inverted erroneous data value. The control logic is to cause the inverted erroneous data value to be stored in the data storage location and subsequently read from the data storage location to produce an operand value. The operating logic is to perform a logical operation using the erroneous data value and the operand value. The evaluation logic is to evaluate the result to determine if the error is a soft error.Type: GrantFiled: August 3, 2007Date of Patent: June 29, 2010Assignee: Intel CorporationInventors: Jaume Abella, Javier Carretero Casado, Xavier Vera