Abstract: The method of performing braiding operations can include providing a first Josephson junction including first gates. The method can include providing a second Josephson junction including second gates. The method can include tuning the first gates to dispose a first pair of Majorana fermions a first region. The method can include tuning the second gates to dispose a second pair of Majorana fermions in a second region. The method can include tuning the first gates to dispose a first Majorana fermion in the first region and to dispose a second Majorana fermion in a third region. The method can include tuning the second gates to dispose a third Majorana fermion in a fourth region and to dispose a fourth Majorana fermion in the second region.

Abstract: A method of fabricating a superconducting-semiconducting stack includes cleaning a surface of a substrate, the substrate comprising a group IV element; depositing an insulating buffer layer onto the substrate, the insulating buffer layer comprising the group IV element; depositing a p-doped layer onto the insulating buffer layer; depositing a diffusion barrier onto the p-doped layer; and processing the superconducting-semiconducting stack through dopant activation.

Abstract: The method of performing braiding operations can include providing a first Josephson junction including first gates. The method can include providing a second Josephson junction including second gates. The method can include tuning the first gates to dispose a first pair of Majorana fermions a first region. The method can include tuning the second gates to dispose a second pair of Majorana fermions in a second region. The method can include tuning the first gates to dispose a first Majorana fermion in the first region and to dispose a second Majorana fermion in a third region. The method can include tuning the second gates to dispose a third Majorana fermion in a fourth region and to dispose a fourth Majorana fermion in the second region.

Abstract: A method of fabricating a superconducting-semiconducting stack includes cleaning a surface of a substrate, the substrate comprising a group IV element; depositing an insulating buffer layer onto the substrate, the insulating buffer layer comprising the group IV element; depositing a p-doped layer onto the insulating buffer layer; depositing a diffusion barrier onto the p-doped layer; and processing the superconducting-semiconducting stack through dopant activation.

Abstract: A method of fabricating a superconducting-semiconducting stack includes cleaning a surface of a substrate, the substrate comprising a group IV element; depositing an insulating buffer layer onto the substrate, the insulating buffer layer comprising the group IV element; depositing a p-doped layer onto the insulating buffer layer; depositing a diffusion barrier onto the p-doped layer; and processing the superconducting-semiconducting stack through dopant activation.

Abstract: An exemplary tundable capacitor in a quantum system includes a pair of qubits, and a capacitive coupling element coupled between the pair of qubits. The capacitive coupling element includes a plurality of gate terminals. The capacitive coupling element is configured to receive a respective gate voltage at each of the plurality of gate terminals and to adjust a capacitance of the capacitive coupling element in response to the respective gate voltage received at each of the plurality of gate terminals. The capacitance of the capacitive coupling element is configured to control a coupling strength between the pair of qubits.

Abstract: The method of performing braiding operations can include providing a first Josephson junction including first gates. The method can include providing a second Josephson junction including second gates. The method can include tuning the first gates to dispose a first pair of Majorana fermions a first region. The method can include tuning the second gates to dispose a second pair of Majorana fermions in a second region. The method can include tuning the first gates to dispose a first Majorana fermion in the first region and to dispose a second Majorana fermion in a third region. The method can include tuning the second gates to dispose a third Majorana fermion in a fourth region and to dispose a fourth Majorana fermion in the second region.

Abstract: A method of fabricating a superconducting-semiconducting stack includes cleaning a surface of a substrate, the substrate comprising a group IV element; depositing an insulating buffer layer onto the substrate, the insulating buffer layer comprising the group IV element; depositing a p-doped layer onto the insulating buffer layer; depositing a diffusion barrier onto the p-doped layer; and processing the superconducting-semiconducting stack through dopant activation.