Patents by Inventor Javier A. FALCON
Javier A. FALCON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955434Abstract: Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.Type: GrantFiled: July 8, 2022Date of Patent: April 9, 2024Assignee: Intel CorporationInventors: Yoshihiro Tomita, Eric J. Li, Shawna M. Liff, Javier A. Falcon, Joshua D. Heppner
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Patent number: 11881457Abstract: Various embodiments disclosed relate to a semiconductor package. The present semiconductor package includes a substrate. The substrate is formed from alternating conducting layers and dielectric layers. A first active electronic component is disposed on an external surface of the substrate, and a second active electronic component is at least partially embedded within the substrate. A first interconnect region is formed from a plurality of interconnects between the first active electronic component and the second active electronic component. Between the first active electronic component and the substrate a second interconnect region is formed from a plurality of interconnects. Additionally, a third interconnect region is formed from a plurality of interconnects between the second active electronic component and the substrate.Type: GrantFiled: March 4, 2021Date of Patent: January 23, 2024Assignee: Tahoe Research, Ltd.Inventors: Adel A. Elsherbini, Johanna M. Swan, Shawna M. Liff, Henning Braunisch, Krishna Bharath, Javier Soto Gonzalez, Javier A. Falcon
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Publication number: 20220344273Abstract: Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.Type: ApplicationFiled: July 8, 2022Publication date: October 27, 2022Inventors: Toshihiro TOMITA, Eric J. LI, Shawna M. LIFF, Javier A. FALCON, Joshua D. HEPPNER
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Publication number: 20220246554Abstract: Embodiments of the invention include a microelectronic device that includes a first silicon based substrate having compound semiconductor components. The microelectronic device also includes a second substrate coupled to the first substrate. The second substrate includes an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher.Type: ApplicationFiled: April 14, 2022Publication date: August 4, 2022Inventors: Telesphor KAMGAING, Georgios C. DOGIAMIS, Vijay K. NAIR, Javier A. FALCON, Shawna M. LIFF, Yoshihiro TOMITA
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Patent number: 11387200Abstract: Embodiments of the invention include a microelectronic device that includes a first die formed with a silicon based substrate and a second die coupled to the first die. The second die is formed with compound semiconductor materials in a different substrate (e.g., compound semiconductor substrate, group III-V substrate). An antenna unit is coupled to the second die. The antenna unit transmits and receives communications at a frequency of approximately 4 GHz or higher.Type: GrantFiled: March 23, 2020Date of Patent: July 12, 2022Assignee: Intel CorporationInventors: Georgios C. Dogiamis, Telesphor Kamgaing, Javier A. Falcon, Yoshihiro Tomita, Vijay K. Nair
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Publication number: 20220199449Abstract: Described herein are carrier assemblies, and related devices and methods. In some embodiments, a carrier assembly includes a carrier; a textured material including texturized microstructures coupled to the carrier; and microelectronic components mechanically coupled to the texturized microstructures. In some embodiments, a carrier assembly includes a carrier having a front side and a back side; an electrode on the front side of the carrier; a dielectric material on the electrode; a charging contact on the back side coupled to the electrode; and microelectronic components electrostatically coupled to the front side of the carrier. In some embodiments, a carrier assembly includes a carrier having a front side and a back side; electrodes on the front side; a dielectric material including texturized microstructures on the electrodes; charging contacts on the back side coupled to the plurality of electrodes; and microelectronic components mechanically and electrostatically coupled to the front side of the carrier.Type: ApplicationFiled: December 23, 2020Publication date: June 23, 2022Applicant: Intel CorporationInventors: Michael J. Baker, Shawna M. Liff, Javier A. Falcon
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Patent number: 11335651Abstract: Embodiments of the invention include a microelectronic device that includes a first silicon based substrate having compound semiconductor components. The microelectronic device also includes a second substrate coupled to the first substrate. The second substrate includes an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher.Type: GrantFiled: December 22, 2015Date of Patent: May 17, 2022Assignee: Intel CorporationInventors: Telesphor Kamgaing, Georgios C. Dogiamis, Vijay K. Nair, Javier A. Falcon, Shawna M. Liff, Yoshihiro Tomita
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Patent number: 11296052Abstract: A device package has substrates disposed on top of one another to form a stack, and pads formed on at least one of the top surface and the bottom surface of each of the substrates. The device package has interconnects electrically coupling at least one of the top surface and the bottom surface of each substrate to at least one of the top surface and the bottom surface of another substrate. The device package has pillars disposed between at least one of the top surface and the bottom surface of one or more substrates to at least one of the top surface and the bottom surface of other substrates. The device package also has adhesive layers formed between at least one of the top surface and the bottom surface of one or more substrates to at least one of the top surface and the bottom surface of other substrates.Type: GrantFiled: September 30, 2017Date of Patent: April 5, 2022Assignee: Intel CorporationInventors: Preston T. Meyers, Javier A. Falcon, Shawna M. Liff, Joe R. Saucedo, Adel A. Elsherbini, Albert S. Lopez, Johanna M. Swan
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Patent number: 11177912Abstract: One aspect of the present disclosure provides a quantum circuit assembly that includes a substrate with one or more qubit devices, and at least one demultiplexer included in a single chip with the qubit device(s). The demultiplexer is configured to receive a combined signal from external electronics, the combined signal including a combination of a plurality of signals in different frequency ranges, and to demultiplex said plurality of signals within the combined signal. The demultiplexer is further configured to apply different demultiplexed signals to different lines of a single qubit device, or/and to different qubit devices. Providing such demultiplexers on-chip with the qubit devices advantageously allows reducing the number of input/output lines coupling the chip with qubit devices and the external electronics.Type: GrantFiled: March 6, 2018Date of Patent: November 16, 2021Assignee: Intel CorporationInventors: Adel A. Elsherbini, Javier A. Falcon, Lester Lampert
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Publication number: 20210193583Abstract: Various embodiments disclosed relate to a semiconductor package. The present semiconductor package includes a substrate. The substrate is formed from alternating conducting layers and dielectric layers. A first active electronic component is disposed on an external surface of the substrate, and a second active electronic component is at least partially embedded within the substrate. A first interconnect region is formed from a plurality of interconnects between the first active electronic component and the second active electronic component. Between the first active electronic component and the substrate a second interconnect region is formed from a plurality of interconnects. Additionally, a third interconnect region is formed from a plurality of interconnects between the second active electronic component and the substrate.Type: ApplicationFiled: March 4, 2021Publication date: June 24, 2021Inventors: Adel A. ELSHERBINI, Johanna M. SWAN, Shawna M. LIFF, Henning BRAUNISCH, Krishna BHARATH, Javier SOTO GONZALEZ, Javier A. FALCON
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Patent number: 10971453Abstract: Various embodiments disclosed relate to a semiconductor package. The present semiconductor package includes a substrate. The substrate is formed from alternating conducting layers and dielectric layers. A first active electronic component is disposed on an external surface of the substrate, and a second active electronic component is at least partially embedded within the substrate. A first interconnect region is formed from a plurality of interconnects between the first active electronic component and the second active electronic component. Between the first active electronic component and the substrate a second interconnect region is formed from a plurality of interconnects. Additionally, a third interconnect region is formed from a plurality of interconnects between the second active electronic component and the substrate.Type: GrantFiled: September 30, 2016Date of Patent: April 6, 2021Assignee: Intel CorporationInventors: Adel A. Elsherbini, Johanna M. Swan, Shawna M. Liff, Henning Braunisch, Krishna Bharath, Javier Soto Gonzalez, Javier A. Falcon
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Publication number: 20200286834Abstract: Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.Type: ApplicationFiled: May 20, 2020Publication date: September 10, 2020Inventors: Tomita YOSHIHIRO, Eric J. LI, Shawna M. LIFF, Javier A. FALCON, Joshua D. HEPPNER
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Patent number: 10756004Abstract: Quantum computing assemblies with through-hole dies, and related devices and methods, are disclosed herein. For example, in some embodiments, a quantum computing assembly may include a package substrate, a quantum processing die, and a through-hole die between the package substrate and the quantum processing die, wherein the quantum processing die is electrically coupled to the package substrate by interconnects extending through through-holes of the through-hole die.Type: GrantFiled: March 28, 2019Date of Patent: August 25, 2020Assignee: Intel CorporationInventors: Adel A. Elsherbini, Javier A. Falcon, David J. Michalak
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Publication number: 20200227366Abstract: Embodiments of the invention include a microelectronic device that includes a first die formed with a silicon based substrate and a second die coupled to the first die. The second die is formed with compound semiconductor materials in a different substrate (e.g., compound semiconductor substrate, group III-V substrate). An antenna unit is coupled to the second die. The antenna unit transmits and receives communications at a frequency of approximately 4 GHz or higher.Type: ApplicationFiled: March 23, 2020Publication date: July 16, 2020Inventors: Georgios C. DOGIAMIS, Telesphor KAMGAING, Javier A. FALCON, Yoshihiro TOMITA, Vijay K. NAIR
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Patent number: 10707171Abstract: Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.Type: GrantFiled: December 22, 2015Date of Patent: July 7, 2020Assignee: Intel CorporationInventors: Tomita Yoshihiro, Eric J. Li, Shawna M. Liff, Javier A. Falcon, Joshua D. Heppner
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Publication number: 20200212012Abstract: A device package has substrates disposed on top of one another to form a stack, and pads formed on at least one of the top surface and the bottom surface of each of the substrates. The device package has interconnects electrically coupling at least one of the top surface and the bottom surface of each substrate to at least one of the top surface and the bottom surface of another substrate. The device package has pillars disposed between at least one of the top surface and the bottom surface of one or more substrates to at least one of the top surface and the bottom surface of other substrates. The device package also has adhesive layers formed between at least one of the top surface and the bottom surface of one or more substrates to at least one of the top surface and the bottom surface of other substrates.Type: ApplicationFiled: September 30, 2017Publication date: July 2, 2020Inventors: Preston T. MEYERS, Javier A. FALCON, Shawna M. LIFF, Joe R. SAUCEDO, Adel A. ELSHERBINI, Albert S. LOPEZ, Johanna M. SWAN
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Patent number: 10629551Abstract: Embodiments of the invention include a microelectronic device that includes a first die formed with a silicon based substrate and a second die coupled to the first die. The second die is formed with compound semiconductor materials in a different substrate (e.g., compound semiconductor substrate, group III-V substrate). An antenna unit is coupled to the second die. The antenna unit transmits and receives communications at a frequency of approximately 4 GHz or higher.Type: GrantFiled: December 22, 2015Date of Patent: April 21, 2020Assignee: Intel CorporationInventors: Georgios C. Dogiamis, Telesphor Kamgaing, Javier A. Falcon, Yoshihiro Tomita, Vijay K. Nair
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Patent number: 10573608Abstract: Embodiments of the invention include a microelectronic device that includes a first die having a silicon based substrate and a second die coupled to the first die. In one example, the second die is formed with compound semiconductor materials. The microelectronic device includes a substrate that is coupled to the first die with a plurality of electrical connections. The substrate including an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher.Type: GrantFiled: December 22, 2015Date of Patent: February 25, 2020Assignee: Intel CorporationInventors: Georgios C. Dogiamis, Telesphor Kamgaing, Eric J. Li, Javier A. Falcon, Yoshihiro Tomita, Vijay K. Nair, Shawna M. Liff
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Patent number: 10468578Abstract: An exemplary superconducting qubit device package includes a qubit die housing a superconducting qubit device that includes at least one resonator, and a package substrate, each having a first face and an opposing second face. The resonator is disposed on the first face of the qubit die. The first face of the qubit die faces and is attached to the second face of the package substrate by first level interconnects. The second face of the package substrate includes a superconductor facing at least portions of the resonator. Such a package architecture may advantageously allow reducing design complexity and undesired coupling, enable inclusion of larger numbers of qubit devices in the qubit die of the package, reduce potential negative impact of the materials used in the package substrate on resonator performance, and limit some sources of qubit decoherence.Type: GrantFiled: February 20, 2018Date of Patent: November 5, 2019Assignee: Intel CorporationInventors: Adel A. Elsherbini, Javier A. Falcon, Roman Caudillo, James S. Clarke
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Publication number: 20190259705Abstract: Various embodiments disclosed relate to a semiconductor package. The present semiconductor package includes a substrate. The substrate is formed from alternating conducting layers and dielectric layers. A first active electronic component is disposed on an external surface of the substrate, and a second active electronic component is at least partially embedded within the substrate. A first interconnect region is formed from a plurality of interconnects between the first active electronic component and the second active electronic component. Between the first active electronic component and the substrate a second interconnect region is formed from a plurality of interconnects. Additionally, a third interconnect region is formed from a plurality of interconnects between the second active electronic component and the substrate.Type: ApplicationFiled: September 30, 2016Publication date: August 22, 2019Inventors: Adel A. Elsherbini, Johanna M. Swan, Shawna M. Liff, Henning Braunisch, Krishna Bharath, Javier Soto Gonzalez, Javier A. Falcon