Patents by Inventor Javier A. Solis

Javier A. Solis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Universal services multiplexer and time-based interleaving of multiple streams
    Patent number: 9967601
    Abstract: Interleaving multiple streams of data using a universal services multiplexer is followed by conveying a time interleaved multiplexer stream to a remote QAM module. A universal services multiplexer interleaves multiple streams of data into a time interleaved multiplexer stream.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: May 8, 2018
    Assignee: Aurora Networks, Inc.
    Inventors: Michael Field, Javier A Solis, Rei Chen Brockett, Dave Baran
  • Universal Services Multiplexer and Time-Based Interleaving of Multiple Streams
    Publication number: 20150020130
    Abstract: Interleaving multiple streams of data using a universal services multiplexer is followed by conveying a time interleaved multiplexer stream to a remote QAM module. A universal services multiplexer interleaves multiple streams of data into a time interleaved multiplexer stream.
    Type: Application
    Filed: May 13, 2014
    Publication date: January 15, 2015
    Inventors: Michael Field, Javier A Solis, Rei Chen Brockett, Dave Baran
  • Apparatus and method for producing pulse width modulated signals from digital information
    Patent number: 4931751
    Abstract: An apparatus is provided which is responsive to a multiple bit sample of digital information for producing a pulse width modulated signal, the apparatus comprising: a first signal match detector, responsive to a first subset of the multiple bit sample, for producing a first signal that can transition between first and second logical states; a second signal match detector, responsive to a second subset of the multiple bit sample, for producing a second signal that can transition between the first and second logical states; and a voltage summing circuit for producing a first voltage that is substantially proportional to a magnitude of the first signal in one of the first logical state and the second logical state and for producing a second voltage that is substantially proportional to a magnitude of the second signal in one of the first logical state and the second logical state and for producing an output voltage that is substantially proportional to a sum of the first voltage and the second voltage.
    Type: Grant
    Filed: June 2, 1989
    Date of Patent: June 5, 1990
    Assignee: Epyx, Inc.
    Inventors: Glenn J. Keller, Javier A. Solis