Patents by Inventor Javier Alejandro Salcedo
Javier Alejandro Salcedo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230221360Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.Type: ApplicationFiled: March 22, 2023Publication date: July 13, 2023Inventors: Alan J. O'Donnell, David Aherne, Javier Alejandro Salcedo, David J. Clarke, John A. Cleary, Patrick Martin McGuinness, Albert C. O'Grady
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Patent number: 11644497Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.Type: GrantFiled: November 23, 2021Date of Patent: May 9, 2023Assignee: Analog Devices International Unlimited CompanyInventors: Alan J. O'Donnell, David Aherne, Javier Alejandro Salcedo, David J. Clarke, John A. Cleary, Patrick Martin McGuinness, Albert C. O'Grady
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Patent number: 11569658Abstract: High voltage clamps with transient activation and activation release control are provided herein. In certain configurations, an integrated circuit (IC) includes a clamp electrically connected between a first node and a second node and having a control input. The IC further includes a first resistor-capacitor (RC) circuit that activates a detection signal in response to detecting a transient overstress event between the first node and the second node, an active feedback circuit that provides feedback from the first node to the control input of the clamp in response to activation of the detection signal, a second RC circuit that activates a shutdown signal after detecting passage of the transient overstress event based on low pass filtering a voltage difference between the first node and the second node, and a clamp shutdown circuit that turns off the clamp via the control input in response to activation of the shutdown signal.Type: GrantFiled: July 10, 2020Date of Patent: January 31, 2023Assignee: Analog Devices, Inc.Inventors: Srivatsan Parthasarathy, Javier Alejandro Salcedo, James Zhao
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Publication number: 20220082605Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.Type: ApplicationFiled: November 23, 2021Publication date: March 17, 2022Inventors: Alan J. O'Donnell, David Aherne, Javier Alejandro Salcedo, David J. Clarke, John A. Cleary, Patrick Martin McGuinness, Albert C. O'Grady
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Patent number: 11193967Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.Type: GrantFiled: January 15, 2020Date of Patent: December 7, 2021Assignee: Analog Devices GlobalInventors: Alan J. O'Donnell, David Aherne, Javier Alejandro Salcedo, David J. Clarke, John A. Cleary, Patrick Martin McGuinness, Albert C. O'Grady
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Patent number: 10861845Abstract: In certain configurations, an input/output (IO) interface of a semiconductor chip includes a pin, an interface switch connected to the pin, and an overstress detection and active control circuit that controls a resistance of the interface switch with active feedback. The overstress detection and active control circuit increases a resistance of the interface switch in response to detection of a transient overstress event between a first node and a second node. Accordingly, the overstress detection and active control circuit provides separate detection and logic control to selectively modify the resistance of the interface switch such that the interface switch operates with low resistance during normal operating conditions and with high resistance during overstress conditions.Type: GrantFiled: December 6, 2016Date of Patent: December 8, 2020Assignee: Analog Devices, Inc.Inventors: Javier Alejandro Salcedo, Srivatsan Parthasarathy
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Publication number: 20200343721Abstract: High voltage clamps with transient activation and activation release control are provided herein. In certain configurations, an integrated circuit (IC) includes a clamp electrically connected between a first node and a second node and having a control input. The IC further includes a first resistor-capacitor (RC) circuit that activates a detection signal in response to detecting a transient overstress event between the first node and the second node, an active feedback circuit that provides feedback from the first node to the control input of the clamp in response to activation of the detection signal, a second RC circuit that activates a shutdown signal after detecting passage of the transient overstress event based on low pass filtering a voltage difference between the first node and the second node, and a clamp shutdown circuit that turns off the clamp via the control input in response to activation of the shutdown signal.Type: ApplicationFiled: July 10, 2020Publication date: October 29, 2020Inventors: Srivatsan Parthasarathy, Javier Alejandro Salcedo, James Zhao
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Patent number: 10734806Abstract: High voltage clamps with active activation and activation-release control are provided herein. In certain configurations, a clamp can have scalable operating clamping voltage level and can be used to protect the electrical circuit connected to a power supply of a semiconductor chip from damage from an overstress event, such as electrostatic discharge (ESD) events. The pins of the power supply are actively monitored to detect when an overstress event is present, and the clamp is turned-on in response to detecting the overstress event. A timer is used to shut down the clamp after a time delay from detecting the overstress event, thereby providing a false detection shutdown mechanism that prevents the protection clamp from getting falsely activated and remain in the on-state during normal circuit operation.Type: GrantFiled: July 21, 2016Date of Patent: August 4, 2020Assignee: Analog Devices, Inc.Inventors: James Zhao, Javier Alejandro Salcedo, Srivatsan Parthasarathy
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Patent number: 10700056Abstract: A communication interface protection device includes a first electrical overstress (EOS) protection switch electrically connected to a first terminal and a second EOS protection switch electrically connected to a second terminal. Each of the first and second EOS protection switches includes a first semiconductor-controlled rectifier (SCR) and a second SCR and a first diode having a cathode electrically connected to an anode of the first SCR and a second diode having a cathode electrically connected to an anode of the second SCR. The first EOS protection device is configured to be activated in response to an EOS condition that causes a first bias between the first and second terminals, and wherein the second EOS protection device is configured to be activated in response to an EOS condition that causes a second bias between the first and second terminals.Type: GrantFiled: September 7, 2018Date of Patent: June 30, 2020Assignee: ANALOG DEVICES, INC.Inventors: James Zhao, Javier Alejandro Salcedo, Srivatsan Parthasarathy
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Publication number: 20200158771Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.Type: ApplicationFiled: January 15, 2020Publication date: May 21, 2020Inventors: Alan J. O'Donnell, David Aherne, Javier Alejandro Salcedo, David J. Clarke, John A. Cleary, Patrick Martin McGuinness, Albert C. O'Grady
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Patent number: 10608431Abstract: Electrical overstress protection via silicon controlled rectifier (SCR) trigger amplification control is provided. In certain configurations, an overstress protection circuit includes a control circuit for detecting presence of an overstress event between a first pad and a second pad of an interface, and a discharge circuit electrically connected between the first pad and the second pad and selectively activated by the control circuit. The interface corresponds to an electronic interface of an integrated circuit (IC), a System on a Chip (SoC), or System in-a-Package (SiP). The discharge circuit includes a first smaller SCR and a second larger SCR. In response to detecting an overstress event, the control circuit activates the smaller SCR, which in turn activates the larger SCR to provide clamping between the first pad and the second pad.Type: GrantFiled: October 26, 2017Date of Patent: March 31, 2020Assignee: Analog Devices, Inc.Inventors: Linfeng He, Javier Alejandro Salcedo, Srivatsan Parthasarathy
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Publication number: 20200083212Abstract: A communication interface protection device includes a first electrical overstress (EOS) protection switch electrically connected to a first terminal and a second EOS protection switch electrically connected to a second terminal. Each of the first and second EOS protection switches includes a first semiconductor-controlled rectifier (SCR) and a second SCR and a first diode having a cathode electrically connected to an anode of the first SCR and a second diode having a cathode electrically connected to an anode of the second SCR. The first EOS protection device is configured to be activated in response to an EOS condition that causes a first bias between the first and second terminals, and wherein the second EOS protection device is configured to be activated in response to an EOS condition that causes a second bias between the first and second terminals.Type: ApplicationFiled: September 7, 2018Publication date: March 12, 2020Inventors: James Zhao, Javier Alejandro Salcedo, Srivatsan Parthasarathy
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Patent number: 10557881Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.Type: GrantFiled: November 1, 2017Date of Patent: February 11, 2020Assignee: Analog Devices GlobalInventors: Alan J. O'Donnell, David Aherne, Javier Alejandro Salcedo, David J. Clarke, John A. Cleary, Patrick Martin McGuinness, Albert C. O'Grady
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Patent number: 10404059Abstract: Distributed switches to suppress transient electrical overstress-induced latch-up are provided. In certain configurations, an integrated circuit (IC) or semiconductor chip includes a transient electrical overstress detection circuit that activates a transient overstress detection signal in response to detecting a transient electrical overstress event between a pair of power rails. The IC further includes mixed-signal circuits and latch-up suppression switches distributed across the IC, and the latch-up suppression switches temporarily clamp the power rails to one another in response to activation of the transient overstress detection signal to inhibit latch-up of the mixed-signal circuits.Type: GrantFiled: February 9, 2017Date of Patent: September 3, 2019Assignee: Analog Devices, Inc.Inventors: Javier Alejandro Salcedo, Srivatsan Parthasarathy, Linfeng He, Yuanzhong Zhou
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Patent number: 10319714Abstract: High voltage drain-extended metal-oxide-semiconductor (DEMOS) bipolar switches for electrical overstress protection are provided. In certain configurations herein, an electrical overstress switch embodiment for providing electrical overstress protection, such as electrostatic discharge/electrical overstress (ESD/EOS) protection includes both a DEMOS device and an embedded bipolar device. The switch is implemented to achieve the advantages provided by the combined conduction of DEMOS and bipolar devices. For example, the DEMOS device provides surface conduction at the gate region for relatively fast switch device turn on and low voltage overshoot, while the bipolar device provides high current conduction during stress condition and a high holding voltage characteristics to prevent latch-up in mission critical integrated circuit applications.Type: GrantFiled: January 24, 2017Date of Patent: June 11, 2019Assignee: ANALOG DEVICES, INC.Inventors: Sirui Luo, Javier Alejandro Salcedo
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Publication number: 20190128939Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.Type: ApplicationFiled: November 1, 2017Publication date: May 2, 2019Inventors: Alan J. O'Donnell, David Aherne, Javier Alejandro Salcedo, David J. Clarke, John A. Cleary, Patrick Martin McGuinness, Albert C. O'Grady
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Publication number: 20190131787Abstract: Electrical overstress protection via silicon controlled rectifier (SCR) trigger amplification control is provided. In certain configurations, an overstress protection circuit includes a control circuit for detecting presence of an overstress event between a first pad and a second pad of an interface, and a discharge circuit electrically connected between the first pad and the second pad and selectively activated by the control circuit. The interface corresponds to an electronic interface of an integrated circuit (IC), a System on a Chip (SoC), or System in-a-Package (SiP). The discharge circuit includes a first smaller SCR and a second larger SCR. In response to detecting an overstress event, the control circuit activates the smaller SCR, which in turn activates the larger SCR to provide clamping between the first pad and the second pad.Type: ApplicationFiled: October 26, 2017Publication date: May 2, 2019Inventors: Linfeng He, Javier Alejandro Salcedo, Srivatsan Parthasarathy
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Patent number: 10249609Abstract: An integrated circuit device for protecting circuits from transient electrical events is disclosed. An integrated circuit device includes a first bipolar junction transistor (BJT) and a second BJT cross-coupled with the first BJT to operate as a first semiconductor-controlled rectifier (SCR), where a base of the first BJT is connected to a collector of the second BJT, and a base of the second BJT is connected to an emitter or a collector of the first BJT. The integrated circuit device additionally includes a triggering device comprising a first diode having a cathode electrically connected to the base of the first BJT. The integrated circuit device further includes a third BJT cross-coupled with the second BJT to operate as a second SCR, where the third BJT has a collector connected to the base of the second BJT and a base connected to the collector of the second BJT.Type: GrantFiled: August 10, 2017Date of Patent: April 2, 2019Assignee: Analog Devices, Inc.Inventors: Javier Alejandro Salcedo, Linfeng He
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Publication number: 20190051646Abstract: An integrated circuit device for protecting circuits from transient electrical events is disclosed. An integrated circuit device includes a first bipolar junction transistor (BJT) and a second BJT cross-coupled with the first BJT to operate as a first semiconductor-controlled rectifier (SCR), where a base of the first BJT is connected to a collector of the second BJT, and a base of the second BJT is connected to an emitter or a collector of the first BJT. The integrated circuit device additionally includes a triggering device comprising a first diode having a cathode electrically connected to the base of the first BJT. The integrated circuit device further includes a third BJT cross-coupled with the second BJT to operate as a second SCR, where the third BJT has a collector connected to the base of the second BJT and a base connected to the collector of the second BJT.Type: ApplicationFiled: August 10, 2017Publication date: February 14, 2019Inventors: Javier Alejandro Salcedo, Linfeng He
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Patent number: 10199369Abstract: Apparatus and methods for transient overstress protection with false condition shutdown are provided herein. In certain configurations, a high-voltage tolerant actively-controlled protection circuit includes a transient overstress detection circuit, a clamp circuit electrically connected between a first node and a second node, a bias circuit that biases the clamp circuit, and a false condition shutdown circuit. The transient overstress detection circuit generates a detection signal indicating whether or not a transient overstress event is detected between the first and second nodes. Additionally, the false condition shutdown circuit generates a false condition shutdown signal based on low pass filtering a voltage difference between the first and second nodes, thereby determining independently whether or not power is present. The bias circuit controls operation of the clamp circuit in an on state or an off state based on the detection signal and the false condition shutdown signal.Type: GrantFiled: March 4, 2016Date of Patent: February 5, 2019Assignee: Analog Devices, Inc.Inventors: Srivatsan Parthasarathy, Javier Alejandro Salcedo