Abstract: A test switching circuit for a high speed data interface is disclosed. Test switching circuit for a high speed data interface of an integrated circuit including switching transistors which switch in a test mode a termination resistor output stage of a data transmission signal path to a termination resistor input stage of a data reception signal path to form an internal feedback test loop within said integrated circuit.

Abstract: An analogue amplifier with multiplexing capability, without the need to incorporate a multiplexor, comprising an input port, a test input port, an output port, a control input to switch the amplifier between a normal amplifying mode and a test mode, wherein a analogue signal introduced to the input port is amplified to the output port in normal mode, and a test signal on the test port is routed to the output port when the amplifier is in test mode.

Abstract: Test switching circuit for a high speed data interface (1) of an integrated circuit comprising switching transistors (T1-T6) which switch in a test mode a termination resistor output stage (15) of a data transmission signal path (17) to a termination resistor input stage (18) of a data reception signal path (25) to form an internal feedback test loop within said integrated circuit.

Abstract: A process and a device are proposed for testing a serializer and deserializer circuit arrangement, where to control the test sequence a simple digital interface is used. To test the serializer circuit arrangement firstly the quality of a multiphase clock signal of the serializer circuit arrangement and secondly the ability to transmit a preset bit pattern are tested. To test the deserializer circuit arrangement the quality of the multiphase clock signal and the quality of a data eye obtained during clock and data recovery are tested together with the quality of the clock recovery.

Abstract: Analogue amplifier with multiplexing capability comprising an input port (2) for receiving an analogue signal (S); a test input port (3) for receiving a test signal (T); an output port (5); a control input (4) for receiving a test control signal (CRTL-mode) switching the amplifier (1) between a normal amplifying mode and a test mode; wherein in the normal amplifying mode the analogue signal (S) is amplified and transmitted via said output port (5); wherein in the test mode the test signal (T) is routed to said output port (5).

Abstract: A fully differential analogue circuit is tested by monitoring the currents in two branches when a common mode signal is applied and indicating correct operation if the two currents are correlated. A part of the circuit (T20,T21,S1,S2,S3,S4) is modified during test and currents through transistors (T20,T21) are monitored by means of a current mirror and current subtractor arrangement (T213,T214,T215,T216). A voltage (VRL) is produced that, with correlation of the currents, will be approximately mid way between the power supply rails and when mis-correlation occurs will tend to one of the supply rails. The voltage (VRL) is applied to a first amplifier (T219,T221) and to a second amplifier (T222,T223) having a different threshold value from the first amplifier. The outputs of the amplifiers will have opposite logic values if the voltage (VRL) lies between their threshold voltages and the EXOR gate 9 will give a logic 1 output indicating proper circuit function.