Patents by Inventor Javier Ayala

Javier Ayala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210278611
    Abstract: One illustrative device disclosed herein includes a V-groove in a base semiconductor layer of a semiconductor-on-insulator (SOI) substrate, wherein the V-groove is adapted to have a fiber optics cable positioned therein, and an optical component positioned above the V-groove. The device also includes a first layer of silicon dioxide positioned above the optical component, a second layer of silicon dioxide positioned on and in contact with the first layer of silicon dioxide and a third layer of silicon dioxide positioned on and in contact with the second layer of silicon dioxide.
    Type: Application
    Filed: March 3, 2020
    Publication date: September 9, 2021
    Inventors: Asli Sahin, Colleen Meagher, Thomas Houghton, Bo Peng, Karen Nummy, Javier Ayala, Yusheng Bian
  • Patent number: 8592308
    Abstract: A method of forming a semiconductor device includes forming a silicide contact region of a field effect transistor (FET); forming a shallow impurity region in a top surface of the silicide contact region; and forming a stressed liner over the FET such that the shallow impurity region is located at an interface between the silicide contact region and the stressed liner, wherein the shallow impurity region comprises one or more impurities, and is configured to hinder diffusion of silicon within the silicide contact region and prevent morphological degradation of the silicide contact region.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: November 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Javier Ayala, Christian Lavoie, Ahmet S. Ozcan
  • Publication number: 20130020616
    Abstract: A method of forming a semiconductor device includes forming a silicide contact region of a field effect transistor (FET); forming a shallow impurity region in a top surface of the silicide contact region; and forming a stressed liner over the FET such that the shallow impurity region is located at an interface between the silicide contact region and the stressed liner, wherein the shallow impurity region comprises one or more impurities, and is configured to hinder diffusion of silicon within the silicide contact region and prevent morphological degradation of the silicide contact region.
    Type: Application
    Filed: July 20, 2011
    Publication date: January 24, 2013
    Applicant: International Business Machines Corporation
    Inventors: Javier Ayala, Christian Lavoie, Ahmet S. Ozcan
  • Patent number: 7881891
    Abstract: A system and method for optimizing and implementing a metrology sampling plan. A system is provided that includes a system for collecting historical metrology data from a metrology tool; and a reduction analysis system that compares an initial capability calculated from the historical metrology data with a recalculated capability for a reduced data set, wherein the reduced data set is obtained by removing a subset of data from the historical metrology data.
    Type: Grant
    Filed: January 9, 2009
    Date of Patent: February 1, 2011
    Assignee: International Business Machines Corporation
    Inventors: Javier A. Ayala, Marc J. Postiglione, Eric P. Solecky
  • Publication number: 20090119049
    Abstract: A system and method for optimizing and implementing a metrology sampling plan. A system is provided that includes a system for collecting historical metrology data from a metrology tool; and a reduction analysis system that compares an initial capability calculated from the historical metrology data with a recalculated capability for a reduced data set, wherein the reduced data set is obtained by removing a subset of data from the historical metrology data.
    Type: Application
    Filed: January 9, 2009
    Publication date: May 7, 2009
    Inventors: Javier A. Ayala, Marc J. Postiglione, Eric P. Solecky
  • Publication number: 20090066844
    Abstract: Two measurements spaced a shorter time apart than a stabilization period are made of a TV display and used to access a predicted white balance adjustment database to return white balance offsets for entry into the TV.
    Type: Application
    Filed: November 29, 2007
    Publication date: March 12, 2009
    Inventors: Javier Ayala, Oscar Martinez
  • Patent number: 7487054
    Abstract: A system and method for optimizing and implementing a metrology sampling plan. A system is provided that includes a system for collecting historical metrology data from a metrology tool; and a reduction analysis system that compares an initial capability calculated from the historical metrology data with a recalculated capability for a reduced data set, wherein the reduced data set is obtained by removing a subset of data from the historical metrology data.
    Type: Grant
    Filed: May 11, 2005
    Date of Patent: February 3, 2009
    Assignee: International Business Machines Corporation
    Inventors: Javier A. Ayala, Marc J. Postiglione, Eric P. Solecky
  • Publication number: 20060259279
    Abstract: A system and method for optimizing and implementing a metrology sampling plan. A system is provided that includes a system for collecting historical metrology data from a metrology tool; and a reduction analysis system that compares an initial capability calculated from the historical metrology data with a recalculated capability for a reduced data set, wherein the reduced data set is obtained by removing a subset of data from the historical metrology data.
    Type: Application
    Filed: May 11, 2005
    Publication date: November 16, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Javier Ayala, Marc Postiglione, Eric Solecky