Patents by Inventor Javier Diaz
Javier Diaz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240104502Abstract: Disclosed herein is a networked computer system, method, and computer program product for forming a consortium of a general contractor and subcontractors in an online work platform that enter into a contract with a client to complete a work project. In an embodiment, the consortium is a single legal entity with liability protection for the consortium (e.g., a registered LLC). The system processor automatedly generates a signed client's contract and signed subcontractors' contracts with the consortium when the client transmits approval of a general contractor's draft proposal. When the work project is amended, such as by adding a milestone or task, the system processor automatedly generates signed addendums to the client's contract with the consortium, and between the general contractor/consortium and existing subcontractor(s), or generates a new signed contract if a new subcontractor is hired. The system then generates and stores a PDF version of the signed contracts with addendums.Type: ApplicationFiled: September 22, 2023Publication date: March 28, 2024Applicant: Vicoland GmbHInventors: Javier Diaz Jimenez, Alexander McCullagh, Enrique Leon-Prado, Andreas Habsburg-Lothringen
-
Patent number: 11930808Abstract: A method to obtain a composition comprising an enriched population of functional mesenchymal stem cells for hypothermic transport and local administration of said enriched population of functional mesenchymal stem cells in therapy. Finally also described is the use of said enriched population of functional mesenchymal stem cells, and compositions comprising them, obtained by the described method, in autologous or allogeneic treatment of diseases susceptible to mesenchymal stem cell therapy, either by local or systemic treatments, and more particularly in the treatment of osteoarticular diseases such as degenerative disc disease, osteoarthritis, and bone repair; in lupus erythematosus, graft-versus-host disease, and other autoimmune diseases; in peripheral vascular insufficiency and other cardiovascular diseases.Type: GrantFiled: September 18, 2019Date of Patent: March 19, 2024Assignees: UNIVERSIDAD DE VALLADOLID, CITOSPIN, S.L.Inventors: Ana Sánchez García, Francisco Javier García-Sancho Martín, Verónica García Díaz, Mercedes Alberca Zaballos, Sandra Güemes Gutiérrez
-
Patent number: 11920559Abstract: A floating platform for high-power wind turbines, comprising a concrete substructure, said concrete substructure forming the base of the platform, which remains semi-submerged in the operating position, and consisting of a square lower slab on which a series of beams and five hollow reinforced concrete cylinders are constructed, distributed at the corners and the center of said lower slab; a metal superstructure supported on the concrete substructure and forming the base for connection with the wind turbine tower, said tower being coupled at the center thereof; and metal covers covering each of the cylinders, on which the metal superstructure is supported and to which vertical pillars are secured, linked together by beams, which join at the central pillar by an element whereon the base of the wind turbine tower is secured.Type: GrantFiled: December 28, 2018Date of Patent: March 5, 2024Assignees: DRAGADOS S.A., FHECOR INGENIEROS Y CONSULTORES S.A.Inventors: Miguel Vazquez Romero, Noelia Gonzalez Patiño, Elena Martin Diaz, Alejandro Perez Caldentey, José María Ortolano Gonzalez, Raúl Guanche Garcia, Victor Ayllon Martinez, Francisco Ballester Muñoz, Jokin Rico Arenal, Marcos Cerezo Laza, Iñigo Javier Losada Rodríguez
-
Patent number: 11887242Abstract: Circuitry comprises ray tracing circuitry comprising a plurality of floating-point circuitries to perform floating-point processing operations to detect intersection between a virtual ray defined by a ray direction and a test region, the floating-point circuitries operating to a given precision to generate an output floating-point value comprising a significand and an exponent; in which at least some of the plurality of floating-point circuitries are configured to round using a predetermined directed rounding mode any denormal floating-point value generated by operation of that circuitry so as to output normal values, a denormal floating-point value being a floating-point value in which the significand comprises one or more leading zeroes.Type: GrantFiled: June 30, 2021Date of Patent: January 30, 2024Assignee: Arm LimitedInventors: Harsha Valsaraju, Javier Diaz Bruguera
-
Publication number: 20230410219Abstract: A networked computer system, method, and software for an online work platform with a trusted independent payment system that allows a client to hire a contractor online, who subsequently breaks a job into multiple tasks that can be performed by different subcontractors, also hired online. The client is only billed for each task, not for each subcontractor; and the work platform computes and adds in all taxes and fees. Once all of the subcontractors that are assigned to a task submit their work, it must be approved by the contractor and then the client before the client is billed in one invoice for all of the work performed. The client can pay via credit/debit card, or via an escrow account, to a trusted third-party financial services system, which then automatedly and concurrently pays the associated fees, e.g., taxes, the online work platform fee, the contractor fee, and each freelancer fee.Type: ApplicationFiled: June 17, 2023Publication date: December 21, 2023Applicant: Vicoland GmbHInventors: Javier Diaz Jimenez, Alexander McCullagh, Enrique Leon-Prado, Andreas Habsburg-Lothringen
-
Publication number: 20230305805Abstract: Apparatus, method and non-transitory computer-readable medium to store computer-readable code for fabrication of an apparatus. The apparatus comprises instruction decode circuitry to decode instructions and processing circuitry to execute the instructions decoded by the instruction decode circuitry.Type: ApplicationFiled: March 22, 2022Publication date: September 28, 2023Inventors: Harsha VALSARAJU, David Raymond LUTZ, Javier Diaz BRUGUERA
-
Publication number: 20230266942Abstract: A data processing apparatus is provided, which includes addition circuitry that performs a calculation of a sum of a first operand and a second operand. The addition circuitry produces an intermediate data prior to the calculation completing. Determination circuitry uses the intermediate data to produce the sum of the first operand and the second operand plus 1. Further determination circuitry configured to use the intermediate data to produce the sum of the first operand and the second operand plus 2.Type: ApplicationFiled: February 24, 2022Publication date: August 24, 2023Inventors: Javier Diaz BRUGUERA, David Raymond LUTZ, Thomas ELMER, Nicholas Andrew PFISTER
-
Patent number: 11718452Abstract: A stopper holder device for bottles is provided that includes a base-part associated with a bottle neck, a latch articulated in the base-part respect to which can swing, and a bracket which supports the stopper and which is articulated at the latch. The base-part includes an elastically deformable portion with means to release the elastically deformable portion from the bottle neck when causing an elastic deformation on the deformable portion, or to embrace the portion to the neck of the bottle when not causing the elastic deformation, so that the same stopper can be used in different bottles. The base-part also includes first structures, where the latch is articulated, and slots for housing wings of the bracket when the bottle is closed. The bracket includes second structures to which the latch is swingly attached. The latch includes third structures cooperating with the first structures and fourth structures cooperating with the second structures.Type: GrantFiled: October 12, 2020Date of Patent: August 8, 2023Assignee: OIOKY DRINKS, S. L.Inventor: José Javier Diaz Cirauqui
-
Publication number: 20230018056Abstract: A data processing apparatus that converts a plurality of signed digits representing an input value in redundant representation comprises receiver circuitry to receive, at each of a plurality of iterations, a signed digit from the plurality of signed digits, and previous intermediate data from a previous iteration. Concatenation circuitry performs a concatenation of bits corresponding to the signed digit and bits of the previous intermediate data to produce updated intermediate data. Output circuitry provides the updated intermediate data as previous intermediate data of a next iteration. The previous intermediate data comprises S3[i] in non-redundant representation, which is at least part of the input value multiplied by 3 in non-redundant representation.Type: ApplicationFiled: June 27, 2022Publication date: January 19, 2023Inventor: Javier Diaz BRUGUERA
-
Publication number: 20230018977Abstract: A data processing apparatus to perform a digit-recurrence operation on an input value comprises receiver circuitry for receiving a remainder value of a previous iteration of the digit-recurrence operation. Comparison circuitry performs comparisons on most significant bits of the remainder value of the previous iteration of the digit-recurrence operation with each of a plurality of selection constants associated with available digits of a next digit of a result of the digit-recurrence operation and outputs the next digit of the result of the digit-recurrence operation based on the comparisons. Each of the selection constants is associated with one of the available digits and an input parameter. Storage circuitry stores a subset of the selection constants, the subset of the selection constants excluding an excluded selection constant from the selection constants, which is associated with an excluded digit from the available digits.Type: ApplicationFiled: June 27, 2022Publication date: January 19, 2023Inventor: Javier Diaz BRUGUERA
-
Publication number: 20230017462Abstract: An apparatus comprises combined divide/square root processing circuitry to perform, in response to a divide instruction, a given radix-64 iteration of a radix-64 divide operation, and in response to a square root instruction, a given radix-64 iteration of a radix-64 square root operation; in which: the combined divide/square root processing circuitry comprises shared circuitry to generate at least one output value for the given radix-64 iteration on a same data path used for both the radix-64 divide operation and the radix-64 square root operation.Type: ApplicationFiled: June 27, 2022Publication date: January 19, 2023Inventor: Javier Diaz BRUGUERA
-
Publication number: 20230013054Abstract: Square root processing circuitry performs a given radix-r iteration of a radix-r square root operation, by performing multiple radix-n sub-iterations in a same processing cycle, where n<r. The square root processing circuitry comprises, for a given radix-n sub-iteration: digit selection circuitry to select, based on a previous remainder estimate, a next radix-n result digit for a square root result; remainder update circuitry to adjust a previous remainder value to generate an updated remainder value; and remainder estimate circuitry to generate an updated remainder estimate indicative of an estimate of a portion of the updated remainder value. In a final radix-n sub-iteration of the given radix-r iteration, the remainder estimate circuitry generates the updated remainder estimate in parallel with the remainder update circuitry generating the updated remainder value.Type: ApplicationFiled: June 27, 2022Publication date: January 19, 2023Inventor: Javier Diaz BRUGUERA
-
Publication number: 20230005209Abstract: Circuitry comprises ray tracing circuitry comprising a plurality of floating-point circuitries to perform floating-point processing operations to detect intersection between a virtual ray defined by a ray direction and a test region, the floating-point circuitries operating to a given precision to generate an output floating-point value comprising a significand and an exponent; in which at least some of the plurality of floating-point circuitries are configured to round using a predetermined directed rounding mode any denormal floating-point value generated by operation of that circuitry so as to output normal values, a denormal floating-point value being a floating-point value in which the significand comprises one or more leading zeroes.Type: ApplicationFiled: June 30, 2021Publication date: January 5, 2023Inventors: Harsha VALSARAJU, Javier Diaz Bruguera
-
Patent number: 11500612Abstract: The present disclosure relates generally to arithmetic units of processors, and may relate more particularly to multi-cycle division operations. Multiple-cycles of a radix-m division operation may be performed to generate one or more signal states representative of a result value based at least in part on a dividend value and a divisor value.Type: GrantFiled: February 14, 2020Date of Patent: November 15, 2022Assignee: Arm LimitedInventor: Javier Diaz Bruguera
-
Patent number: 11281428Abstract: A data processing apparatus is provided to convert a plurality of signed digits to an output value, the data processing apparatus comprising: receiver circuitry to receive, at each of a plurality of iterations, a signed digit from the plurality of signed digits, and previous intermediate data. Conversion circuitry performs a negative-output conversion from the signed digit to an unsigned digit, such that the output value comprising the unsigned digit is negative. Concatenation circuitry concatenate bits of the unsigned digit and bits of the previous intermediate data to produce updated intermediate data and output circuitry provides the updated intermediate data as the previous intermediate data of a next iteration. After the plurality of iterations, the output circuitry outputs at least part of the updated intermediate data as the output value.Type: GrantFiled: March 12, 2019Date of Patent: March 22, 2022Assignee: ARM LIMITEDInventor: Javier Diaz Bruguera
-
Publication number: 20220079965Abstract: A therapeutic use of acylated piceid derivative compounds in ocular pathologies, in particular retinitis pigmentosa and in age-related macular degeneration, inter alia. A method of treating and/or preventing ocular pathologies, wherein the method includes administering to a patient in need of treatment a therapeutically effective amount of a compound of general formula (I) or any of its isomers, their pharmaceutically acceptable salts, esters, tautomers, polymorphs, or hydrates.Type: ApplicationFiled: November 30, 2021Publication date: March 17, 2022Inventors: Juan Carlos MORALES SÁNCHEZ, Pablo PEÑALVER PUENTE, Francisco Javier DÍAZ CORRALES, María Lourdes VALDÉS SÁNCHEZ, Ana Belén GARCÍA DELGADO, Adoración MONTERO SÁNCHEZ
-
Patent number: 11213536Abstract: The present invention relates to the therapeutic use of acylated piceid derivative compounds in ocular pathologies, in particular retinitis pigmentosa and in age-related macular degeneration.Type: GrantFiled: November 17, 2017Date of Patent: January 4, 2022Assignees: CONSEJO SUPERIOR DE INVESTIGACIONES CIENTIFICAS, FUNDACION PUBLICA ANDALUZA PROGRESO Y SALUDInventors: Juan Carlos Morales Sánchez, Pablo Peñalver Puente, Francisco Javier Díaz Corrales, María Lourdes Valdés Sánchez, Ana Belén García Delgado, Adoración Montero Sánchez
-
Patent number: 11119731Abstract: A data processing apparatus is provided to convert a plurality of signed digits to an output value. Receiver circuitry receives, at each of a plurality of iterations, one of the plurality of signed digits, each of the signed digits comprising a number of bits dependent on a radix. The signed digits being used to form an unrounded output value followed by zero or more extra bits. Adjustment circuitry adjusts a least-significant digit of the unrounded output value to produce an incremented unrounded output value after the plurality of iterations. Rounding circuitry selects from among the unrounded output value and the incremented unrounded output value to produce the output value. The adjustment circuitry is adapted, when a value of a position of a least-significant bit of the unrounded output value is greater than or equal to the radix divided by two, to adjust a subset of the digits of the unrounded output value.Type: GrantFiled: August 26, 2019Date of Patent: September 14, 2021Assignee: ARM LIMITEDInventor: Javier Diaz Bruguera
-
Patent number: 11097349Abstract: The method comprises the steps of: a) supplying building material; and b) fusing the building material using a light beam (2); wherein steps a) and b) are carried out so as to progressively produce the object out of the fused building material. In step b), the beam (2) is projected onto the building material so as to produce a primary spot on the building material, the beam being repetitively scanned in two dimensions in accordance with a first scanning pattern so as to establish an effective spot (21) on the building material, said effective spot having a two-dimensional energy distribution. The effective spot (21) is displaced in relation to the object being produced to progressively produce the object by fusing the building material.Type: GrantFiled: May 12, 2020Date of Patent: August 24, 2021Assignee: ETXE-TAR, S.A.Inventors: Javier Diaz, Jesus Dominguez, Paula Sancho
-
Publication number: 20210255831Abstract: The present disclosure relates generally to arithmetic units of processors, and may relate more particularly to multi-cycle division operations.Type: ApplicationFiled: February 14, 2020Publication date: August 19, 2021Inventor: Javier Diaz Bruguera