Patents by Inventor Javier Soto Gonzalez

Javier Soto Gonzalez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • FORMING DIE BACKSIDE COATING STRUCTURES WITH CORELESS PACKAGES
    Publication number: 20130252376
    Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a patterned die backside film (DBF) on a backside of a die, wherein the patterned DBF comprises an opening surrounding at least one through silicon via (TSV) pad disposed on the backside of the die.
    Type: Application
    Filed: May 16, 2013
    Publication date: September 26, 2013
    Inventors: Rahul N. Manepalli, Mohit Mamodia, David Xu, Javier Soto Gonzalez, Edward R. Prack
  • SUBSTRATE WITH EMBEDDED STACKED THROUGH-SILICON VIA DIE
    Publication number: 20130147043
    Abstract: A substrate with an embedded stacked through-silicon via die is described. For example, an apparatus includes a first die and a second die. The second die has one or more through-silicon vias disposed therein (TSV die). The first die is electrically coupled to the TSV die through the one or more through-silicon vias. The apparatus also includes a coreless substrate. Both the first die and the TSV die are embedded in the coreless substrate.
    Type: Application
    Filed: February 1, 2013
    Publication date: June 13, 2013
    Inventors: Javier Soto Gonzalez, Houssam Jomaa
  • Substrate with embedded stacked through-silicon via die
    Patent number: 8421245
    Abstract: A substrate with an embedded stacked through-silicon via die is described. For example, an apparatus includes a first die and a second die. The second die has one or more through-silicon vias disposed therein (TSV die). The first die is electrically coupled to the TSV die through the one or more through-silicon vias. The apparatus also includes a coreless substrate. Both the first die and the TSV die are embedded in the coreless substrate.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: April 16, 2013
    Assignee: Intel Corporation
    Inventors: Javier Soto Gonzalez, Houssam Jomaa
  • SUBSTRATE WITH EMBEDDED STACKED THROUGH-SILICON VIA DIE
    Publication number: 20120161316
    Abstract: A substrate with an embedded stacked through-silicon via die is described. For example, an apparatus includes a first die and a second die. The second die has one or more through-silicon vias disposed therein (TSV die). The first die is electrically coupled to the TSV die through the one or more through-silicon vias. The apparatus also includes a coreless substrate. Both the first die and the TSV die are embedded in the coreless substrate.
    Type: Application
    Filed: December 22, 2010
    Publication date: June 28, 2012
    Inventors: Javier Soto Gonzalez, Houssam Jomaa
  • MULTI-CHIP PACKAGE HAVING A SUBSTRATE WITH A PLURALITY OF VERTICALLY EMBEDDED DIE AND A PROCESS OF FORMING THE SAME
    Publication number: 20120161331
    Abstract: An apparatus includes a substrate having a land side having a plurality of contact pads and a die side opposite the land side. The apparatus includes a first die and a second die wherein the first die and second die are embedded within the substrate such that the second die is located between the first die and the land side of the substrate.
    Type: Application
    Filed: December 22, 2010
    Publication date: June 28, 2012
    Inventors: Javier Soto Gonzalez, Houssam Jomaa
  • DIE-STACKING USING THROUGH-SILICON VIAS ON BUMPLESS BUILD-UP LAYER SUBSTRATES INCLUDING EMBEDDED-DICE, AND PROCESSES OF FORMING SAME
    Publication number: 20120074581
    Abstract: An apparatus includes a coreless substrate with a through-silicon via (TSV) embedded die that is integral to the coreless substrate. The apparatus includes a subsequent die that is coupled to the TSV die and that is disposed above the coreless substrate.
    Type: Application
    Filed: September 24, 2010
    Publication date: March 29, 2012
    Inventors: John S. Guzek, Ravi K. Nalla, Javier Soto Gonzalez, Drew Delaney, Suresh Pothukuchi, Mohit Mamodia, Edward Zarbock, Johanna M. Swan
  • FORMING FUNCTIONALIZED CARRIER STRUCTURES WITH CORELESS PACKAGES
    Publication number: 20110254124
    Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material.
    Type: Application
    Filed: April 16, 2010
    Publication date: October 20, 2011
    Inventors: Ravi K. Nalla, John Guzek, Javier Soto Gonzalez, Drew Delaney, Hamid Azimi
  • Semiconductor package with embedded die and its methods of fabrication
    Publication number: 20110215464
    Abstract: Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that contains the embedded die. The semiconductor package provides die stacking or package stacking capabilities. Furthermore, embodiments of the present invention describe a method of fabricating the semiconductor package that minimizes assembly costs.
    Type: Application
    Filed: December 29, 2009
    Publication date: September 8, 2011
    Inventors: John Stephen Guzek, Javier Soto Gonzalez, Nicholas R. Watts, Ravi K. Nalla
  • Semiconductor device with package to package connection
    Patent number: 7952182
    Abstract: A semiconductor package comprises a first package; a second package that is provided on the first package; and a first interconnect that comprises a bump to couple to the first package and a base material layer to cover the bump, wherein the second package is supported on the base material layer that is coupled to the bump.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: May 31, 2011
    Assignee: Intel Corporation
    Inventors: Nicholas Randolph Watts, Javier Soto Gonzalez
  • Coreless substrate package with symmetric external dielectric layers
    Publication number: 20090321932
    Abstract: A thin die Package Substrate is described that may be produced using existing chemistry. In one example, a package substrate is built over a support material. A dry film photoresist layer is formed over the package substrate. The support material is removed from the package substrate. The dry film photoresist layer is removed from the substrate and the substrate is finished for use with a package.
    Type: Application
    Filed: June 30, 2008
    Publication date: December 31, 2009
    Inventors: Javier Soto Gonzalez, Tao Wu, Pallavi Alur, Mihir Roy, Sheng Li, Reynaldo Olmedo