Abstract: Double-heterostructure (DH) diode lasers based upon very thin epitaxial layers of Ga.sub.x In.sub.1-x As.sub.y P.sub.1-y grown on and lattice-matched to oriented InP substrates are disclosed. A preferred method for fabricating such lasers involves the successive growth, on an InP substrate, of an InP buffer layer, the GaInAsP active layer and an InP top barrier layer using liquid phase epitaxy techniques to grow these layers from supercooled solutions. Stripe geometry lasers can be fabricated from these materials which emit in the 1.1-1.3 .mu.m range and are capable of cw operation for extended periods at room temperature.

Abstract: Double-heterostructure (DH) diode lasers based upon very thin epitaxial layers of Ga.sub.x In.sub.1-x As.sub.y P.sub.1-y grown on and lattice-matched to oriented InP substrates are disclosed. A preferred method for fabricating such lasers involves the successive growth, on an InP substrate, of an InP buffer layer, the GaInAsP active layer and an InP top barrier layer using liquid phase epitaxy techniques to grow these layers from supercooled solutions. Stripe geometry lasers can be fabricated from these materials which emit in the 1.1-1.3 .mu.m range and are capable of cw operation for extended periods at room temperature.

Abstract: An improved avalanche photodiode having an active layer of Ga.sub.x In.sub.1-x As.sub.y P.sub.1-y containing a p-n junction and a window layer grown epitaxially to an n.sup.+ substrate is disclosed herein, as well as methods for its fabrication.

Abstract: A uniform and thin layer of a semiconductor is grown on a semiconductor substrate by an improved liquid phase epitaxy growth method. The growth solution is supercooled and is pushed rapidly over the substrate on which the layer of solute is grown. In GaAs the amount of supercooling is typically 3.degree. to 5.degree. C. and a constant thickness ultra-thin layer (about 0.18 microns) is grown on top of a GaAs substrate.

Abstract: A memory cell having three MOS transistors and four external connecting lines, and suitable for fabrication in an array of memory cells forming rows and columns on an LSI chip, is organized into a stack of chips to form a three dimensional random-access read-write memory system. The memory array is organized so that each memory cell on the chip provides capacitive storage for a binary digit of a different word and a single digit is written into or read from a selected memory cell of a single chip or array as a word is written into, or read from, the memory system. The memory cells of each chip are arranged in a matrix of rows and columns, whereby a limited number of semiconductors are required in the memory array to form the capacitive storage memory cells and connecting selection circuitry.