Patents by Inventor Jaw-Kang Her

Jaw-Kang Her has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7421383
    Abstract: Semiconductor device junction simulation is carried out utilizing models that are developed with series resistance extractions that improve their fidelity particularly in the high current regions of device operation. The models may also be tailored to account for geometric considerations of the semiconductor devices thereby allowing for a more flexible model and simulation by providing for geometric scaling capabilities.
    Type: Grant
    Filed: January 15, 2003
    Date of Patent: September 2, 2008
    Assignee: Taiwan Semiconductor Mfg Co, Ltd
    Inventors: Cheng Hsiao, Ke-Wei Su, Jaw-Kang Her
  • Patent number: 7141485
    Abstract: A method for reducing sidewall capacitance by 25% or more in an STI structure is described. A conformal barrier layer is deposited on sloped sidewalls in a shallow trench within a substrate. The trench is filled with a low k dielectric material which is planarized and etched back. Next a barrier cap layer is deposited that is different than the underlying low k dielectric layer. In one embodiment, the barrier cap layer is a SiCOH material that is modified for enhanced CMP performance that yields fewer surface scratches and defects. A nitride etch stop layer and a pad oxide are removed above an active area on the substrate to afford the final STI structure. Optionally, the barrier cap layer is omitted and the low k dielectric layer extends slightly above the substrate level. Total parasitic capacitance in the resulting MOS device is reduced by 15% or more.
    Type: Grant
    Filed: June 13, 2003
    Date of Patent: November 28, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ke-Wei Su, Cheng Hsiao, Jaw-Kang Her
  • Publication number: 20040251513
    Abstract: A method for reducing sidewall capacitance by 25% or more in an STI structure is described. A conformal barrier layer is deposited on sloped sidewalls in a shallow trench within a substrate. The trench is filled with a low k dielectric material which is planarized and etched back. Next a barrier cap layer is deposited that is different than the underlying low k dielectric layer. In one embodiment, the barrier cap layer is a SiCOH material that is modified for enhanced CMP performance that yields fewer surface scratches and defects. A nitride etch stop layer and a pad oxide are removed above an active area on the substrate to afford the final STI structure. Optionally, the barrier cap layer is omitted and the low k dielectric layer extends slightly above the substrate level. Total parasitic capacitance in the resulting MOS device is reduced by 15% or more.
    Type: Application
    Filed: June 13, 2003
    Publication date: December 16, 2004
    Applicant: Taiwan Semicondutor Manufacturing Co.
    Inventors: Ke-Wei Su, Cheng Hsiao, Jaw-Kang Her
  • Patent number: 6800496
    Abstract: A method of characterizing gate leakage current in the fabrication of integrated circuits is described. A MOSFET model is provided including a gate electrode deposed over a gate oxide layer on a substrate and source and drain regions associated with the gate electrode. Device current is measured at four terminals simultaneously wherein one of the terminals is a drain terminal. The other terminals are the source, gate, and substrate. The portion of the device current measured at the drain terminal that is contributed by gate current is evaluated. The evaluated gate current contribution is subtracted from the drain terminal current measurement to obtain pure drain current. Fitting procedures are performed to obtain curves for the device currents. The pure drain current is used to extract mobility model parameters.
    Type: Grant
    Filed: August 20, 2003
    Date of Patent: October 5, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Shi Chiang, Ke-Wei Su, Chung-Kai Lin, Jaw-Kang Her, Yu-Tai Chia
  • Publication number: 20040138865
    Abstract: Semiconductor device junction simulation is carried out utilizing models that are developed with series resistance extractions that improve their fidelity particularly in the high current regions of device operation. The models may also be tailored to account for geometric considerations of the semiconductor devices thereby allowing for a more flexible model and simulation by providing for geometric scaling capabilities.
    Type: Application
    Filed: January 15, 2003
    Publication date: July 15, 2004
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng Hsiao, Ke-Wei Su, Jaw-Kang Her
  • Publication number: 20030222308
    Abstract: A method for forming an SOI (Silicon-on-Insulator) semiconductor device and a SOI semiconductor device formed thereof, wherein the SOI semiconductor device comprises a source, a drain, and a gate formed upon a substrate. At least one P+ body contact region is generally located adjacent the source and away from a channel of the SOI semiconductor device. At least one poly tee may be connected to the gate, such that the poly tee passes through the P+ body contact region. The P+ body contact region and the source can be connected together on a surface of a silicon film utilizing a silicide, thereby forming the SOI semiconductor device.
    Type: Application
    Filed: May 30, 2002
    Publication date: December 4, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ke-Wei Su, Jaw-Kang Her, Fu-Liang Yang, Yi-Ling Chan