Patents by Inventor Jawad Haj-Yihia

Jawad Haj-Yihia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190011976
    Abstract: Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency. are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: September 13, 2018
    Publication date: January 10, 2019
    Applicant: Intel Corporation
    Inventors: Jawad Haj-Yihia, Eliezer Weissmann, Vijay S. R. Degalahal, Nadav Shulman, Tal Kuzi, Itay Franko, Amit Gur, Efraim Rotem
  • Patent number: 10114448
    Abstract: Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency. are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: October 30, 2018
    Assignee: Intel Corporation
    Inventors: Jawad Haj-Yihia, Eliezer Weissmann, Vijay S R Degalahal, Nadav Shulman, Tal Kuzi, Itay Franko, Amit Gur, Efraim Rotem
  • Patent number: 9766683
    Abstract: A processor includes at least one core, a power control unit, and a first interconnect to couple with a peripheral controller. The first interconnect is to provide a first uni-directional communication path for communication of first power management data from the processor to the peripheral controller. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: September 19, 2017
    Assignee: Intel Corporation
    Inventors: Shaun M. Conrad, William Knolla, Douglas R. Moran, Sm M. Rahman, Jawad Haj-Yihia, Alon Naveh, Ohad Falik
  • Patent number: 9612652
    Abstract: Methods and apparatus relating to controlling power consumption by a power management link are described. In one embodiment, the physical interface of a power management (PM) link is shut down when a processor is in a sleep state (e.g., to conserve power), while maintaining the availability of the processor for communication to a (e.g., embedded) controller over the PM link. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: September 29, 2012
    Date of Patent: April 4, 2017
    Assignee: Intel Corporation
    Inventors: Nir Rosenzweig, Efraim Rotem, Jawad Haj-Yihia, Ohad Falik
  • Publication number: 20170010648
    Abstract: A processor includes at least one core, a power control unit, and a first interconnect to couple with a peripheral controller. The first interconnect is to provide a first uni-directional communication path for communication of first power management data from the processor to the peripheral controller. Other embodiments are described and claimed.
    Type: Application
    Filed: September 20, 2016
    Publication date: January 12, 2017
    Inventors: Shaun M. Conrad, William Knolla, Douglas R. Moran, Sm M. Rahman, Jawad Haj-Yihia, Alon Naveh, Ohad Falik
  • Patent number: 9477627
    Abstract: A processor includes at least one core, a power control unit, and a first interconnect to couple with a peripheral controller. The first interconnect is to provide a first uni-directional communication path for communication of first power management data from the processor to the peripheral controller. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: October 25, 2016
    Assignee: Intel Corporation
    Inventors: Shaun M. Conrad, William Knolla, Douglas R. Moran, SM M. Rahman, Jawad Haj-Yihia, Alon Naveh, Ohad Falik
  • Patent number: 9323307
    Abstract: Power consumption and dissipation is reduced during active display of content from an internal display buffer using a power supply topology that powers a display subsystem separately from the other components of a CPU. The power supply topology enables a processor to enter a sleep state without disabling the active display of content. The processor enters a processor sleep state when the display buffer is full and the processor components are no longer needed. The processor exits the processor sleep state when the display buffer is empty and operates in conjunction with the display subsystem to fill the buffer with more content. The processor continues to enter and exit the processor sleep states as appropriate until active display ends.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: April 26, 2016
    Assignee: Intel Corporation
    Inventor: Jawad Haj-Yihia
  • Patent number: 9274580
    Abstract: Systems and methods may provide for monitoring a current provided from a voltage regulator to a non-core region of a processor, and asserting a throttle signal to the non-core region of the processor if the current exceeds a supply capability threshold of the voltage regulator. In one example, a specified current supply capability of the non-core region is greater than a current supply capability of the voltage regulator, and the supply capability threshold is less than the specified current supply capability of the non-core region and an over current protection threshold of the non-core region.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: March 1, 2016
    Assignee: Intel Corporation
    Inventors: Ruoying Mary Ma, Craig Forbell, Soethiha Soe, Jawad Haj-Yihia, Jeffrey Carlson
  • Patent number: 8924755
    Abstract: Power consumption and dissipation during sleep states of processors is reduced using a novel connected standby sleep state. In the connected standby sleep state a dedicated power plane is used to maintain processor context. To conserve power, unnecessary components on the processor are powered down, including all of the clock components, and wakeup sources previously directed to the processor are directed to a platform control hub. The platform control hub sustains certain architectural functions for the processor during connected standby sleep state, and manages the wakeup logic for returning the processor to the preceding sleep state.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: December 30, 2014
    Assignee: Intel Corporation
    Inventor: Jawad Haj-Yihia
  • Patent number: 8788861
    Abstract: Power consumption and dissipation during sleep states of processors is reduced using a novel connected standby sleep state. In the connected standby sleep state a dedicated power plane is used to maintain processor context. To conserve power, unnecessary components on the processor are powered down, including all of the clock components, and wakeup sources previously directed to the processor are directed to a platform control hub. The platform control hub sustains certain architectural functions for the processor during connected standby sleep state, and manages the wakeup logic for returning the processor to the preceding sleep state.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: July 22, 2014
    Assignee: Intel Corporation
    Inventor: Jawad Haj-Yihia
  • Publication number: 20140181352
    Abstract: A processor includes at least one core, a power control unit, and a first interconnect to couple with a peripheral controller. The first interconnect is to provide a first uni-directional communication path for communication of first power management data from the processor to the peripheral controller. Other embodiments are described and claimed.
    Type: Application
    Filed: December 26, 2012
    Publication date: June 26, 2014
    Inventors: Shaun M. Conrad, William Knolla, Douglas R. Moran, SM M. RAHMAN, JAWAD HAJ-YIHIA, ALON NAVEH, OHAD FALIK
  • Publication number: 20140095911
    Abstract: Methods and apparatus relating to controlling power consumption by a power management link are described. In one embodiment, the physical interface of a power management (PM) link is shut down when a processor is in a sleep state (e.g., to conserve power), while maintaining the availability of the processor for communication to a (e.g., embedded) controller over the PM link. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: September 29, 2012
    Publication date: April 3, 2014
    Inventors: Nir Rosenzweig, Efraim Rotem, Jawad Haj-Yihia, Ohad Falik
  • Publication number: 20140006833
    Abstract: Systems and methods may provide for monitoring a current provided from a voltage regulator to a non-core region of a processor, and asserting a throttle signal to the non-core region of the processor if the current exceeds a supply capability threshold of the voltage regulator. In one example, a specified current supply capability of the non-core region is greater than a current supply capability of the voltage regulator, and the supply capability threshold is less than the specified current supply capability of the non-core region and an over current protection threshold of the non-core region.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 2, 2014
    Inventors: Ruoying Mary Ma, Craig Forbell, Soethiha Soe, Jawad Haj-Yihia
  • Publication number: 20130238918
    Abstract: Power consumption and dissipation during sleep states of processors is reduced using a novel connected standby sleep state. In the connected standby sleep state a dedicated power plane is used to maintain processor context. To conserve power, unnecessary components on the processor are powered down, including all of the clock components, and wakeup sources previously directed to the processor are directed to a platform control hub. The platform control hub sustains certain architectural functions for the processor during connected standby sleep state, and manages the wakeup logic for returning the processor to the preceding sleep state.
    Type: Application
    Filed: May 7, 2013
    Publication date: September 12, 2013
    Inventor: Jawad Haj-Yihia
  • Publication number: 20130191667
    Abstract: Power consumption and dissipation during sleep states of processors is reduced using a novel connected standby sleep state. In the connected standby sleep state a dedicated power plane is used to maintain processor context. To conserve power, unnecessary components on the processor are powered down, including all of the clock components, and wakeup sources previously directed to the processor are directed to a platform control hub. The platform control hub sustains certain architectural functions for the processor during connected standby sleep state, and manages the wakeup logic for returning the processor to the preceding sleep state.
    Type: Application
    Filed: March 12, 2013
    Publication date: July 25, 2013
    Inventor: JAWAD HAJ-YIHIA
  • Patent number: 8458503
    Abstract: Power consumption and dissipation during sleep states of processors is reduced using a novel connected standby sleep state. In the connected standby sleep state a dedicated power plane is used to maintain processor context. To conserve power, unnecessary components on the processor are powered down, including all of the clock components, and wakeup sources previously directed to the processor are directed to a platform control hub. The platform control hub sustains certain architectural functions for the processor during connected standby sleep state, and manages the wakeup logic for returning the processor to the preceding sleep state.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: June 4, 2013
    Assignee: Intel Corporation
    Inventor: Jawad Haj-Yihia
  • Patent number: 8230247
    Abstract: Power consumption and dissipation during sleep states of processors is reduced using a novel connected standby sleep state. In the connected standby sleep state a dedicated power plane is used to maintain processor context. To conserve power, unnecessary components on the processor are powered down, including all of the clock components, and wakeup sources previously directed to the processor are directed to a platform control hub. The platform control hub sustains certain architectural functions for the processor during connected standby sleep state, and manages the wakeup logic for returning the processor to the preceding sleep state.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: July 24, 2012
    Assignee: Intel Corporation
    Inventor: Jawad Haj-Yihia
  • Publication number: 20120102342
    Abstract: Power consumption and dissipation is reduced during active display of content from an internal display buffer using a power supply topology that powers a display subsystem separately from the other components of a CPU. The power supply topology enables a processor to enter a sleep state without disabling the active display of content. The processor enters a processor sleep state when the display buffer is full and the processor components are no longer needed. The processor exits the processor sleep state when the display buffer is empty and operates in conjunction with the display subsystem to fill the buffer with more content. The processor continues to enter and exit the processor sleep states as appropriate until active display ends.
    Type: Application
    Filed: December 30, 2011
    Publication date: April 26, 2012
    Inventor: Jawad Haj-Yihia
  • Publication number: 20120102346
    Abstract: Power consumption and dissipation during sleep states of processors is reduced using a novel connected standby sleep state. In the connected standby sleep state a dedicated power plane is used to maintain processor context. To conserve power, unnecessary components on the processor are powered down, including all of the clock components, and wakeup sources previously directed to the processor are directed to a platform control hub. The platform control hub sustains certain architectural functions for the processor during connected standby sleep state, and manages the wakeup logic for returning the processor to the preceding sleep state.
    Type: Application
    Filed: December 30, 2011
    Publication date: April 26, 2012
    Inventor: Jawad Haj-Yihia