Patents by Inventor Jawahar P. Nayak
Jawahar P. Nayak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10714411Abstract: An IC chip structure including a plurality of IC chips electrically connected to one another in back-end-of-line (BEOL) interconnect layer of the structure is disclosed. The IC structure may include openings in crack-stop structures surrounding the IC chips and a interconnect wire extending between the IC chips through the openings. A packaging structure for utilizing the IC structure where at least one IC chip is inoperable is also disclosed. The structure may include a first bond pad array on a top surface of a packaging substrate including operable bond pads connected to an operable IC chip and structural support bond pads connected to the inoperable IC chip; a second bond pad array on a bottom surface of the substrate including operable bond pads connected to a single IC chip printed circuit board; and an interconnect structure for connecting the operable bond pads of the first and second bond pad arrays.Type: GrantFiled: March 15, 2018Date of Patent: July 14, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Wolfgang Sauter, Mark W. Kuemerle, Eric W. Tremble, David B. Stone, Nicholas A. Polomoff, Eric S. Parent, Jawahar P. Nayak, Seungman Choi
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Publication number: 20190287879Abstract: An IC chip structure including a plurality of IC chips electrically connected to one another in back-end-of-line (BEOL) interconnect layer of the structure is disclosed. The IC structure may include openings in crack-stop structures surrounding the IC chips and a interconnect wire extending between the IC chips through the openings. A packaging structure for utilizing the IC structure where at least one IC chip is inoperable is also disclosed. The structure may include a first bond pad array on a top surface of a packaging substrate including operable bond pads connected to an operable IC chip and structural support bond pads connected to the inoperable IC chip; a second bond pad array on a bottom surface of the substrate including operable bond pads connected to a single IC chip printed circuit board; and an interconnect structure for connecting the operable bond pads of the first and second bond pad arrays.Type: ApplicationFiled: March 15, 2018Publication date: September 19, 2019Inventors: Wolfgang Sauter, Mark W. Kuemerle, Eric W. Tremble, David B. Stone, Nicholas A. Polomoff, Eric S. Parent, Jawahar P. Nayak, Seungman Choi
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Patent number: 7456098Abstract: Stacked via pillars, such as metal via pillars, are provided at different and designated locations in IC chips to support the chip structure during processing and any related processing stresses such as thermal and mechanical stresses. These stacked via pillars connect and extend from a base substrate of the strip to a top oxide cap of the chip. The primary purpose of the stacked via pillars is to hold the chip structure together to accommodate any radial deformations and also to relieve any stress, thermal and/or mechanical, build-tip during processing or reliability testing. The stacked via pillars are generally not electrically connected to any active lines or vias, however in some embodiments the stacked via pillars can provide an additional function of providing an electrical connection in the chip.Type: GrantFiled: April 13, 2006Date of Patent: November 25, 2008Assignee: International Business Machines CorporationInventors: Habib Hichri, Xiao H. Liu, Vincent J. McGahay, Conal E. Murray, Jawahar P. Nayak, Thomas M. Shaw
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Patent number: 7138714Abstract: The present invention provides an interconnect structure that includes a diffusion barrier which is positioned within the structure in a fashion that increases the reliability and lifetime of the interconnect structure.Type: GrantFiled: February 11, 2005Date of Patent: November 21, 2006Assignee: International Business Machines CorporationInventors: Du B. Nguyen, Birendra N. Agarwala, Conrad A Barile, Jawahar P. Nayak, Hazara S. Rathore
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Patent number: 7067902Abstract: Stacked via pillars, such as metal via pillars, are provided at different and designated locations in IC chips to support the chip structure during processing and any related processing stresses such as thermal and mechanical stresses. These stacked via pillars connect and extend from a base substrate of the strip to a top oxide cap of the chip. The primary purpose of the stacked via pillars is to hold the chip structure together to accommodate any radial deformations and also to relieve any stress, thermal and/or mechanical, build-up during processing or reliability testing. The stacked via pillars are generally not electrically connected to any active lines or vias, however in some embodiments the stacked via pillars can provide an additional function of providing an electrical connection in the chip.Type: GrantFiled: December 2, 2003Date of Patent: June 27, 2006Assignee: International Business Machines CorporationInventors: Habib Hichri, Xiao H. Liu, Vincent J. McGahay, Conal E. Murray, Jawahar P. Nayak, Thomas M. Shaw
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Patent number: 6972209Abstract: A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material.Type: GrantFiled: November 27, 2002Date of Patent: December 6, 2005Assignee: International Business Machines CorporationInventors: Birendra N. Agarwala, Conrad A. Barile, Hormazdyar M. Dalal, Brett H. Engle, Michael Lane, Ernest Levine, Xiao Hu Liu, Vincent McGahay, John F. McGrath, Conal E. Murray, Jawahar P. Nayak, Du B. Nguyen, Hazara S. Rathore, Thomas M. Shaw
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Patent number: 6750109Abstract: A semiconductor chip includes a semiconductor substrate having a rectifying contact diffusion and a non-rectifying contact diffusion. A halo diffusion is adjacent the rectifying contact diffusion and no halo diffusion is adjacent the non-rectifying contact diffusion. The rectifying contact diffusion can be a source/drain diffusion of an FET to improve resistance to punch-through. The non-rectifying contact diffusion may be an FET body contact, a lateral diode contact, or a resistor or capacitor contact. Avoiding a halo for non-rectifying contacts reduces series resistance and improves device characteristics. In another embodiment on a chip having devices with halos adjacent diffusions, no halo diffusion is adjacent a rectifying contact diffusion of a lateral diode, significantly improving ideality of the diode and increasing breakdown voltage.Type: GrantFiled: July 1, 2002Date of Patent: June 15, 2004Assignee: International Business Machines CorporationInventors: James A. Culp, Jawahar P. Nayak, Werner A. Rausch, Melanie J. Sherony, Steven H. Voldman, Noah D. Zamdmer
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Publication number: 20040101663Abstract: A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material.Type: ApplicationFiled: November 27, 2002Publication date: May 27, 2004Inventors: Birendra N. Agarwala, Conrad A. Barile, Hormazdyar M. Dalal, Brett H. Engel, Michael Lane, Ernest Levine, Xiao Hu Liu, Vincent McGahay, John F. McGrath, Conal E. Murray, Jawahar P. Nayak, Du B. Nguyen, Hazara S. Rathore, Thomas M. Shaw
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Patent number: 6475555Abstract: A process wherein a low viscosity, metal-containing paste is screened onto a ceramic greensheet and then sets up to increase its viscosity. In one method, the low viscosity is caused by excess solvent which is then blotted or otherwise removed so that the viscosity of the paste is increased. In an alternative method, the low viscosity paste contains a cross-linking agent which causes the paste to increase its viscosity after screening.Type: GrantFiled: October 29, 1999Date of Patent: November 5, 2002Assignee: International Business Machines CorporationInventors: Jon A. Casey, Dinesh Gupta, Lester Wynn Herron, John U. Knickerbocker, David C. Long, Jawahar P. Nayak, Brenda L. Peterson, Robert A. Rita
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Publication number: 20020149058Abstract: A semiconductor chip includes a semiconductor substrate having a rectifying contact diffusion and a non-rectifying contact diffusion. A halo diffusion is adjacent the rectifying contact diffusion and no halo diffusion is adjacent the non-rectifying contact diffusion. The rectifying contact diffusion can be a source/drain diffusion of an FET to improve resistance to punch-through. The non-rectifying contact diffusion may be an FET body contact, a lateral diode contact, or a resistor or capacitor contact. Avoiding a halo for non-rectifying contacts reduces series resistance and improves device characteristics. In another embodiment on a chip having devices with halos adjacent diffusions, no halo diffusion is adjacent a rectifying contact diffusion of a lateral diode, significantly improving ideality of the diode and increasing breakdown voltage.Type: ApplicationFiled: July 1, 2002Publication date: October 17, 2002Applicant: International Business Machines CorporationInventors: James A. Culp, Jawahar P. Nayak, Werner A. Rausch, Melanie J. Sherony, Steven H. Voldman, Noah D. Zamdmer
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Patent number: 6429482Abstract: A semiconductor chip includes a semiconductor substrate having a rectifying contact diffusion and a non-rectifying contact diffusion. A halo diffusion is adjacent the rectifying contact diffusion and no halo diffusion is adjacent the non-rectifying contact diffusion. The rectifying contact diffusion can be a source/drain diffusion of an FET to improve resistance to punch-through. The non-rectifying contact diffusion may be an FET body contact, a lateral diode contact, or a resistor or capacitor contact. Avoiding a halo for non-rectifying contacts reduces series resistance and improves device characteristics. In another embodiment on a chip having devices with halos adjacent diffusions, no halo diffusion is adjacent a rectifying contact diffusion of a lateral diode, significantly improving ideality of the diode and increasing breakdown voltage.Type: GrantFiled: June 8, 2000Date of Patent: August 6, 2002Assignee: International Business Machines CorporationInventors: James A. Culp, Jawahar P. Nayak, Werner A. Rausch, Melanie J. Sherony, Steven H. Voldman, Noah D. Zamdmer
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Publication number: 20020023779Abstract: A method and structure for personalizing a multi-layer substrate structure includes supplying a generic layer having electrical features and altering the electrical features to produce a personalized layer of the multi-layer substrate.Type: ApplicationFiled: October 18, 2001Publication date: February 28, 2002Inventors: Dinesh Gupta, Lester Wynn Herron, John U. Knickerbocker, David C. Long, Jawahar P. Nayak, Keith C. O'Neil, Brenda L. Peterson
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Patent number: 6341417Abstract: A method and structure for personalizing a multi-layer substrate structure includes supplying a generic layer having electrical features and altering the electrical features to produce a personalized layer of the multi-layer substrate.Type: GrantFiled: September 23, 1999Date of Patent: January 29, 2002Assignee: International Business Machines CorporationInventors: Dinesh Gupta, Lester Wynn Herron, John U. Knickerbocker, David C. Long, Jawahar P. Nayak, Keith C. O'Neil, Brenda L. Peterson
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Publication number: 20020009539Abstract: A process wherein a low viscosity, metal-containing paste is screened onto a ceramic greensheet and then sets up to increase its viscosity. In one method, the low viscosity is caused by excess solvent which is then blotted or otherwise removed so that the viscosity of the paste is increased. In an alternative method, the low viscosity paste contains a cross-linking agent which causes the paste to increase its viscosity after screening.Type: ApplicationFiled: October 29, 1999Publication date: January 24, 2002Inventors: JON A. CASEY, DINESH GUPTA, LESTER WYNN HERRON, JOHN U. KNICKERBOCKER, DAVID C. LONG, JAWAHAR P. NAYAK, BRENDA L. PETERSON, ROBERT A. RITA
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Publication number: 20010006116Abstract: A process of forming a multi-layer feature on a ceramic or organic article in which first and second layers of paste are sequentially screened through a screening mask wherein the screening mask has not been moved between screening steps. A structure produced by this process is also disclosed.Type: ApplicationFiled: January 18, 2001Publication date: July 5, 2001Applicant: International Business Machines CorporationInventors: James M. Blazick, Michael E. Cropp, James N. Humenik, Gerald H. Leino, Jawahar P. Nayak, Frank V. Ranalli, Deborah A. Sylvester, John A. Trumpetto, James C. Utter, Rao V. Vallabhaneni, Renne L. Weisman
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Patent number: 6238741Abstract: A process of forming a multi-layer feature on a ceramic or organic article in which first and second layers of paste are sequentially screened through a screening mask wherein the screening mask has not been moved between screening steps. A structure produced by this process is also disclosed.Type: GrantFiled: December 7, 1998Date of Patent: May 29, 2001Assignee: International Business Machines CorporationInventors: James M. Blazick, Michael E. Cropp, James N. Humenik, Gerald H. Leino, Jawahar P. Nayak, Frank V. Ranalli, Deborah A. Sylvester, John A. Trumpetto, James C. Utter, Rao V. Vallabhaneni, Renee L. Weisman
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Patent number: 6231707Abstract: In the formation of multilayer ceramic substrates, greensheets are utilized which have the same pattern and number of vias punched in each greensheet. Then, selected vias may be filled with metallic paste to form the internal connections of the multilayer ceramic substrate. The remaining vias may be filled with a fugitive material or left totally unfilled. Also disclosed is the multilayer ceramic substrate produced by this method.Type: GrantFiled: September 22, 1998Date of Patent: May 15, 2001Assignee: International Business Machines CorporationInventors: Dinesh Gupta, L. Wynn Herron, John U. Knickerbocker, David C. Long, Jawahar P. Nayak, Robert A. Rita
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Patent number: 6221193Abstract: Disclosed is a method for reducing screening defects on ceramic greensheets which includes placing additional vias in the kerf that will be eventually discarded during the sizing operation. Also disclosed is a ceramic substrate laminate article with reduced screening defects.Type: GrantFiled: January 20, 1999Date of Patent: April 24, 2001Assignee: International Business Machines CorporationInventors: Richard J. Cassidy, John R. Lankard, Jr., Jawahar P. Nayak
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Patent number: 5951917Abstract: Deformation of vias and shorting between vias during screening of conductive paste onto greensheets wider than 185 mm is avoided by a concentration of thixotropic agent in the conductive paste formulation to a concentration which raises the thixotropic index of the paste to within 5% to 25% of the maximum achievable thixotropic index for the organic vehicle in the paste. For a paste containing molybdenum powder in which the organic vehicle is a mixture of ethyl cellulose, texanol and oleoyl sarcosine, this criterion corresponds to a concentration of glycerl tri(-12-hydroxystearate) in the range of 1.4% to 1.8% by weight.Type: GrantFiled: March 6, 1998Date of Patent: September 14, 1999Assignee: International Business Machines CorporationInventors: Jawahar P. Nayak, Michael E. Cropp, John M. Wargo, Nancy A. Wier-Cavalieri, Charles W. Hunter, Jr.
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Patent number: 5783113Abstract: Deformation of vias and shorting between vias during screening of conductive paste onto greensheets wider than 185 mm is avoided by a concentration of thixotropic agent in the conductive paste formulation to a concentration which raises the thixotropic index of the paste to within 5% to 25% of the maximum achievable thixotropic index for the organic vehicle in the paste. For a paste containing molybdenum powder in which the organic vehicle is a mixture of ethyl cellulose, texanol and oleoyl sarcosine, this criterion corresponds to a concentration of glycerl tri(-12-hydroxystearate) in the range of 1.4% to 1.8% by weight.Type: GrantFiled: March 27, 1997Date of Patent: July 21, 1998Assignee: International Business Machines CorporationInventors: Jawahar P. Nayak, Michael E. Cropp, John M. Wargo, Nancy A. Wier-Cavalieri, Charles W. Hunter, Jr.