Abstract: In described examples, an integrated circuit includes an output terminal coupled to an input of a power amplifier, a feedback terminal coupled to an output of the power amplifier, a data terminal that receives a data stream, and a digital pre-distortion (DPD) circuit. The DPD circuit includes a capture circuit, a DPD estimator responsive to the data stream and the feedback terminal, and a DPD corrector responsive to the DPD estimator. The DPD estimator includes an instruction memory configured to store instructions and a vector arithmetic processing unit (APU) coupled to the instruction memory. The vector APU includes vector memories, vector arithmetic blocks, and an instruction decode block. The vector arithmetic blocks include vector addition blocks and vector multiplication blocks. The instruction decode block is configured to cause the vector APU to perform complex domain vector arithmetic on vectors stored in the vector memories in response to the instructions.

Abstract: An example apparatus includes: nonlinearity function selection circuitry with an output, the nonlinearity function selection circuitry to select a type of a nonlinearity function, the nonlinearity function to model nonlinearity portions of data output from an analog-to-digital converter, nonlinearity function term generation circuitry with a first input coupled to the output, the nonlinearity function term generation circuitry to generate one or more nonlinearity function terms of the nonlinearity function based on the type of the nonlinearity function and the data, and coefficient determination circuitry with a second input coupled to the output, the coefficient determination circuitry to determine one or more nonlinearity function coefficients based on the one or more nonlinearity function terms, the nonlinearity portions of the data to be compensated based on the one or more nonlinearity function coefficients.

Abstract: A transmitter includes a data stream encoder layer having an output and a pattern generator having a bit pattern output. The transmitter further includes a first multiplexer having first and second inputs and a first multiplexer output. The first input is coupled to the output of the data stream encoder layer, and the second input is coupled to the bit pattern output of the pattern generator. While at least a portion of the data stream encoder layer is powered down, the pattern generator is configured to provide bit patterns on its bit pattern output, a control signal to the first multiplexer is configured to select the second input of the first multiplexer, and the first multiplexer is configured to output the bit patterns on the output of the first multiplexer.

Abstract: Techniques maintaining receiver reliability, including determining a present attenuation level for an attenuator, wherein the attenuation level is set by a gain controller, determining a relative reliability threshold based on the present attenuation level, receiving a radio frequency (RF) signal, determining a voltage level of the received RF signal, comparing the voltage level of the received RF signal to the relative reliability threshold to determine that a reliability condition exists, and overriding, in response to the determination that the reliability condition exists, the present attenuation level set by the gain controller with an override attenuation level based on the present attenuation level.

Abstract: A zero-insertion FIR filter architecture for filtering a signal with a target band and a secondary band. Digital filter circuitry includes an L-tap FIR (finite impulse response) filter, with a number L filter tap elements (L=0, 1, 2, . . . (L?1)), each with an assigned coefficient from a defined coefficient sequence. The L-tap FIR filter is configurable with a defined zero-insertion coefficient sequence of a repeating sub-sequence of a nonzero coefficient followed by one or more zero-inserted coefficients, with a number Nj of nonzero coefficients, and a number Nk of zero-inserted coefficients, so that L=Nj+Nk. The L-tap FIR filter is configurable as an M-tap FIR filter with a nonzero coefficient sequence in which each of the L filter tap elements is assigned a non-zero coefficient, the M-tap FIR filter having an effective length of M=(Nj+Nk) non-zero coefficients.

Abstract: A phase coherent NCO circuit includes a base frequency NCO, a phase seeding circuit, a scaled frequency NCO, a sine/cosine generator. The base frequency NCO is configured to generate base phase values based on a base frequency control word. The phase seeding circuit is coupled to the base frequency NCO. The phase seeding circuit is configured to generate a seed phase value based on the base phase values and a scale factor value. The scaled frequency NCO is coupled to the phase seeding circuit. The scaled frequency NCO is configured to generate oscillator phase values based on the phase seed value and an oscillator frequency control word. The sine/cosine generator is coupled to the scaled frequency NCO. The sine/cosine generator is configured to generate oscillator output samples based on the oscillator phase values.

Abstract: A phase spectrum based delay estimating method of tracking channel responses, extracting phase responses from the tracked channel responses, and generating a delay estimate, wherein the delay estimate is based on a slope and intercept estimates of the extracted phase responses with high quality metric to improve delay estimation, and a system thereof.

Abstract: Techniques maintaining receiver reliability, including determining a present attenuation level for an attenuator, wherein the attenuation level is set by a gain controller, determining a relative reliability threshold based on the present attenuation level, receiving a radio frequency (RF) signal, determining a voltage level of the received RF signal, comparing the voltage level of the received RF signal to the relative reliability threshold to determine that a reliability condition exists, and overriding, in response to the determination that the reliability condition exists, the present attenuation level set by the gain controller with an override attenuation level based on the present attenuation level.

Abstract: An integrated circuit comprises an input, a digital step attenuator, an analog-to-digital converter, a first output, a second output, a first bandwidth filter, a first band attack detector, a first band decay detector, a second bandwidth filter, a second band attack detector, a second band decay detector, and an automatic gain control. The ADC is configured to output a digital signal including a first and a second frequency range. The first and second bandwidth filters are configured to extract respective digital signals comprising the first and second frequency ranges. The band attack and decay detectors are configured to detect band peaks or decays thereof such that the DSA and External AMP may be controlled by means of the AGC based on the detected band peaks or decays, and ADC attack and ADC decay.

Abstract: A channel response generating module and method for generating a channel response based on a ratio of a channel response corresponding to an image signal frequency bin in relation to a channel response corresponding to a traffic signal frequency bin, or a channel response corresponding to a first frequency bin in relation to a channel response corresponding to a second frequency bin, and a zero-IF signal transmitter employing the channel response generating module and method to efficiently suppress image signals or compensate traffic signals during transmission of IQ RF signals.

Abstract: A system includes: a host processor; a transceiver coupled to the host processor; and a power amplifier coupled to an output of the transceiver. The transceiver includes a transmit chain with digital pre-distortion (DPD) logic configured to: perform DPD correction operations on transmit data received by the transmit chain; and output corrected transmit data based on the performed DPD correction operations, wherein the output corrected transmit data is provided to the power amplifier.

Abstract: Techniques maintaining receiver reliability, including determining a present attenuation level for an attenuator, wherein the attenuation level is set by a gain controller, determining a relative reliability threshold based on the present attenuation level, receiving a radio frequency (RF) signal, determining a voltage level of the received RF signal, comparing the voltage level of the received RF signal to the relative reliability threshold to determine that a reliability condition exists, and overriding, in response to the determination that the reliability condition exists, the present attenuation level set by the gain controller with an override attenuation level based on the present attenuation level.

Abstract: A method for non-linearity correction includes receiving a first output signal from a data signal path containing a first analog-to-digital converter and receiving a second output signal from a second analog-to-digital converter. The method also includes generating first non-linearity coefficients using the first output signal and generating second non-linearity coefficients using the first and second output signals. The method further includes applying, by a non-linearity corrector in the data signal path, the first and second non-linearity coefficients to compensate for non-linearity components in a digitized signal output from the first analog-to-digital converter to generate a corrected digitized signal.

Abstract: A non-linearity correction circuit includes a non-linearity coefficient estimation circuit. The non-linearity coefficient estimation circuit includes a data capture circuit, a non-linearity term generation circuit, a time-to-frequency conversion circuit, a bin identification circuit, a residual non-linearity conversion circuit, and a non-linearity coefficient generation circuit. The non-linearity term generation circuit is coupled to the data capture circuit. The time-to-frequency conversion circuit is coupled to the data capture circuit and the non-linearity term generation circuit. The bin identification circuit is coupled to the time-to-frequency conversion circuit. The residual non-linearity conversion circuit is coupled to the bin identification circuit. The non-linearity coefficient generation circuit is coupled to the bin identification circuit and the residual non-linearity conversion circuit.

Abstract: A transmitter includes a data stream encoder layer having an output and a pattern generator having a bit pattern output. The transmitter further includes a first multiplexer having first and second inputs and a first multiplexer output. The first input is coupled to the output of the data stream encoder layer, and the second input is coupled to the bit pattern output of the pattern generator. While at least a portion of the data stream encoder layer is powered down, the pattern generator is configured to provide bit patterns on its bit pattern output, a control signal to the first multiplexer is configured to select the second input of the first multiplexer, and the first multiplexer is configured to output the bit patterns on the output of the first multiplexer.

Abstract: A transmitter includes a data stream encoder layer having an output and a pattern generator having a bit pattern output. The transmitter further includes a first multiplexer having first and second inputs and a first multiplexer output. The first input is coupled to the output of the data stream encoder layer, and the second input is coupled to the bit pattern output of the pattern generator. While at least a portion of the data stream encoder layer is powered down, the pattern generator is configured to provide bit patterns on its bit pattern output, a control signal to the first multiplexer is configured to select the second input of the first multiplexer, and the first multiplexer is configured to output the bit patterns on the output of the first multiplexer.

Abstract: An electrical system includes a transceiver with an IQ estimator and an IQ mismatch corrector. The electrical system also includes an antenna coupled to the transceiver. The IQ estimator is configured to perform frequency-domain IQ mismatch analysis to determine an IQ mismatch estimate at available frequency bins of a baseband data signal. The IQ mismatch corrector is configured to correct the baseband data signal based on the IQ mismatch estimate.

Abstract: A system includes: a host processor; a transceiver coupled to the host processor; and a power amplifier coupled to an output of the transceiver. The transceiver includes a transmit chain with digital pre-distortion (DPD) logic configured to: perform DPD correction operations on transmit data received by the transmit chain; and output corrected transmit data based on the performed DPD correction operations, wherein the output corrected transmit data is provided to the power amplifier.

Abstract: An IQ mismatch estimation circuit includes a raw channel estimation circuit, a reference channel estimation circuit, a digital predistortion (DPD) bin identification circuit, a channel estimate pruning circuit, and an IQ correction coefficient generation circuit. The raw channel estimation circuit generates raw channel estimates for a plurality of frequency bins of a baseband signal. The reference channel estimation circuit identifies a reference channel estimate based on the raw channel estimates. The DPD bin identification circuit identifies, based on the reference channel estimate, the frequency bins for which the raw channel estimates are based on a DPD expansion signal. The channel estimate pruning circuit generates pruned raw channel estimates by discarding the raw channel estimates of the frequency bins identified by the DPD bin identification circuit. The IQ correction coefficient generation circuit generates IQ mismatch correction coefficients based on the pruned raw channel estimates.

Abstract: A non-linearity correction module, an optional droop corrector, and a zero-IF receiver with the non-linearity correction module and an optional droop corrector, wherein the non-linearity correction module is configured to generate a non-linearity term scaled to mitigate an inter-modulation component term of a RF signal received by the zero-IF receiver based on a test signal to enhance linearity in the zero-IF receiver and the optional droop corrector is configured to compensate a droop within a signal band of interest, caused by an analog low pass filter filtering a RF signal received by the zero-IF receiver, before a down-converted RF signal is fed into the non-linearity module.