Abstract: Embodiments are directed to rectifiers using a single bias current or bias current path to bias multiple rectifying elements. A rectifier that has multiple rectifier stages coupled together serially includes a bias current path coupled to each of the rectifier stages. Thee bias current path is configured to simultaneously bias rectifying elements in each of the rectifier stages by using a bias current to bias a first rectifying element and reusing the bias current to bias other rectifying elements.

Abstract: Backflow in rectifiers may be reduced via biasing. Upon determining that backflow within a rectifier is likely, one or more rectifying elements in the rectifier may be debiased, via analog or digital means. The debiased rectifying elements become less conductive or nonconductive, thereby reducing or preventing backflow. The determination of backflow likelihood may be performed based on a signal to be backscattered or the amplitude-modulated envelope of an incident RF wave, and may be digital or analog in nature.

Abstract: Embodiments are directed to rectifiers using a single bias current or bias current path to bias multiple rectifying elements. A rectifier that has multiple rectifier stages coupled together serially includes a bias current path coupled to each of the rectifier stages. The bias current path is configured to simultaneously bias rectifying elements in each of the rectifier stages by using a bias current to bias a first rectifying element and reusing the bias current to bias other rectifying elements.

Abstract: Backflow in rectifiers may be reduced via biasing. Upon determining that backflow within a rectifier is likely, one or more rectifying elements in the rectifier may be debiased, via analog or digital means. The debiased rectifying elements become less conductive or nonconductive, thereby reducing or preventing backflow. The determination of backflow likelihood may be performed based on a signal to be backscattered or the amplitude-modulated envelope of an incident RF wave, and may be digital or analog in nature.

Abstract: Embodiments are directed to mitigating power-based impedance changes in Radio Frequency Identification (RFID) tags. The intrinsic impedance of components in an RFID tag front-end may change as incident RF power on the tag changes, causing the input impedance of the front-end to change and altering the RF properties of the RFID tag. A number of approaches can be used to mitigate input impedance variations due to power variations. One approach involves adjusting the operating point of one or more components in the RFID tag front-end to change their intrinsic impedances so as to counteract or mitigate the RF-power-based input impedance variation.

Abstract: Embodiments are directed to rectifiers using a single bias current or bias current path to bias multiple rectifying elements. A rectifier that has multiple rectifier stages coupled together serially includes a bias current path coupled to each of the rectifier stages. Thee bias current path is configured to simultaneously bias rectifying elements in each of the rectifier stages by using a bias current to bias a first rectifying element and reusing the bias current to bias other rectifying elements.

Abstract: Embodiments are directed to mitigating power-based impedance changes in Radio Frequency Identification (RFID) tags. The intrinsic impedance of components in an RFID tag front-end may change as incident RF power on the tag changes, causing the input impedance of the front-end to change and altering the RF properties of the RFID tag. A number of approaches can be used to mitigate input impedance variations due to power variations. One approach involves adjusting the operating point of one or more components in the RFID tag front-end to change their intrinsic impedances so as to counteract or mitigate the RF-power-based input impedance variation.

Abstract: Embodiments are directed to mitigating power-based impedance changes in Radio Frequency Identification (RFID) tags. The intrinsic impedance of components in an RFID tag front-end may change as incident RF power on the tag changes, causing the input impedance of the front-end to change and altering the RF properties of the RFID tag. A number of approaches can be used to mitigate input impedance variations due to power variations. One approach involves adjusting the operating point of one or more components in the RFID tag front-end to change their intrinsic impedances so as to counteract or mitigate the RF-power-based input impedance variation.

Abstract: The present disclosure provides a power rectifier for a Radio Frequency Identification tag circuit. The power rectifier is constructed from a pair of hybrid RF rectifier elements that include a MOS transistor. Gates of the transistors have predetermined voltages applied to them. The applied voltages bias the transistors to near their active operating regions, while an additional RF control signal is being applied to the gates of the transistors.

Abstract: The present disclosure provides examples of a voltage regulator for a Radio Frequency Identification tag circuit. The voltage regulator includes a pair of native transistors. A first native transistor is coupled to a reference voltage and biased to saturation. A resistive element coupled between the gate and the drain of the transistor ensures a sufficient voltage difference between the source and the drain of the first native transistor. The second native transistor, with a gate coupled to the gate of the first native transistor, outputs a regulated voltage.

Abstract: The present disclosure provides for a voltage reference circuit for Radio Frequency Identification (RFID) tag circuit. Such a circuit is formed in a substrate that is lightly doped with impurities of a first polarity. A first transistor having a first source connected to a ground, a first gate doped with impurities of the first polarity, and a first drain connected to the first gate at a reference node, a reference current source to provide a reference current to the reference node for generating a first reference voltage at the reference node, and an additional component for receiving the first reference voltage are disclosed.

Abstract: Microcircuits may include polysilicon features that are vulnerable to defects due to undesirable phenomena during manufacturing processes such as, inter alia, over-etching. The same phenomena that may cause defects can be exploited to automatically isolate the affected circuit and thus limit the harm caused by defects or incipient defects.

Abstract: Technologies suitable for on-wafer testing in the ubiquitous computing era are disclosed. Among the inventive features disclosed are: 1) clustering of wafer test probe landing area sites for parallel test sequencing; 2) on wafer test wiring that runs along the wafer's scribe regions; 3) on-wafer test wiring that can be scribed and yet thwart the spread of contamination into the product die; 4) an RFID tag design that allows for on-wafer testing without imposing substantial semiconductor surface area penalty; 5) an RFID tag design that includes built-in self test (BIST) circuitry for the RFID tag's non-volatile memory.

Abstract: Technologies suitable for on-wafer testing in the ubiquitous computing era are disclosed. Among the inventive features disclosed are: 1) clustering of wafer test probe landing area sites for parallel test sequencing; 2) on wafer test wiring that runs along the wafer's scribe regions; 3) on-wafer test wiring that can be scribed and yet thwart the spread of contamination into the product die; 4) an RFID tag design that allows for on-wafer testing without imposing substantial semiconductor surface area penalty; 5) an RFID tag design that includes built-in self test (BIST) circuitry for the RFID tag's non-volatile memory.

Abstract: An analog processing block is arranged to receive an input signal through an AC coupling circuit. A digitally programmable voltage reference (DPVR) circuit is arranged to provide selection of a voltage reference that is DC coupled through a high impedance circuit to the AC coupling circuit. The input to the analog processing block includes the AC coupled input signal and the DC level from the selected voltage reference such that the DC level is effectively shifted for the analog processing block. The analog processing block may include any number of analog functions including: buffering, level shifting, scaling, integrating, and analog-to-digital conversion for digital signal processing, to name a few. A digital control logic circuit and a trim map can be arranged to control adjustments to the DPVR such that the effects of any non-ideal conditions on the analog processing block are minimized. The trim map may include non-volatile memory devices.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to (i) select one of a plurality of input signals and (ii) generate (a) an output signal having a frequency and (b) one or more control signals in response to a skew signal. The second circuit may be configured to generate the skew signal in response to the one or more control signals. The first circuit may be configured to minimize skew between the selected input signal and a feedback of the output signal, in response to the skew signal.

Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to receive a first input signal and a second input signal and present a first signal and a second signal. The second circuit may be configured to present a first output signal in response to the first input signal, the first signal and the second signal. The third circuit may be configured to present a second output signal in response to the second input signal, the first signal and the second signal.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate (i) a first intermediate signal in response to a first differential signal and (ii) a second intermediate signal in response to a second differential signal. The second circuit may be configured (i) to generate one or more output signals in response to a relative arrival time of the first and second intermediate signals and (ii) to clamp a later arriving one of the first and second intermediate signals to a predefined voltage level.