Abstract: A wind vane that easily snaps on to golf equipment such as the pole of a golf bag for visually indicating wind direction to a golfer comprises two side elements attached to each other at a junction along the side elements' edges forming approximately a 50 degree angle between the side elements, and a partially opened cylindrical clamp. A ring holder is provided on the inside surface of each of the side elements. A plurality of ribbons extend from each of the ring holders and the movement of such ribbons indicate the direction and to some extent the speed of the wind. An alternate embodiment of the wind vane comprises arms that clip onto a canopy pole of a golf cart and a plurality of ribbons to indicate wind direction.

Abstract: A circuit for obtaining clock timing information from an equalized pseudo-ternary signal, such as is exemplified by a signal using the modified duobinary code, includes a level selector in which the signal is sliced at a predetermined amplitude. A slicing level reference circuit provides the threshold voltage for the level selector so that only the upper level portion of the original is obtained for processing. This upper level portion is applied to an amplifier and then to a frequency selection circuit which is tuned to the clock frequency of the original signal.

Abstract: A buffer amplifier, which prevents loading of the input signal, accepts at its input an amplified and equalized pseudo-ternary signal. The output of the buffer amplifier is a-c coupled to the input of a precision differential amplifier, from which two output signals are obtained. One said output signal is representative of the positive pulses and the other said output signal is representative of the negative pulses of the pseudo-ternary signal. These two output signals are both applied to the inputs of a peak detector and a slicer. The d-c output of the peak detector is also applied as one input to the slicer. Separate outputs are obtained from the slicer, one each for the positive and negative pulse inputs, and these two outputs are summed, and the summed output is then amplified to provide a clock driver output.