Patents by Inventor Jay A. Yoder
Jay A. Yoder has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240098911Abstract: An insulation displacement terminal comprises a first portion, a second portion, and a press-fit pin. The first portion may comprise a first beam and a second beam. A slot is generally formed by a first central edge of the first beam and a second central edge of the second beam. The second portion may comprise a third beam, a fourth beam, and a fifth beam. The fourth beam is configured as a cantilever beam with an attached lower end and a distal end that is able to move between the third beam and the fifth beam. The press-fit pin is generally attached to an edge of the distal end of the fourth beam.Type: ApplicationFiled: September 21, 2022Publication date: March 21, 2024Inventor: Jacob Jay Yoder
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Publication number: 20230317576Abstract: Methods of forming semiconductor packages include providing a lead frame having leads and no tie-bars. Tape is attached to the lead frame and one or more semiconductor die are coupled therewith. Electrical contacts of the die are interconnected with the leads using electrical connectors. An encapsulated assembly is formed by at least partially encapsulating the die and electrical connectors. The assembly is singulated to form a semiconductor package. The tape is detached from the package or encapsulated assembly. One or more die attach flags may be attached to the tape and the die may be attached thereto. Semiconductor packages formed using the methods include one or more semiconductor die at least partially encapsulated, pins exposed through the encapsulant, electrical connectors within the encapsulant and electrically interconnecting the pins with electrical contacts of the die, and no tie-bars coupling the die with the pins. Packages may also include die attach flags.Type: ApplicationFiled: June 6, 2023Publication date: October 5, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Stephen ST. GERMAIN, Jay A. YODER, Dennis Lee CONNER, Frank Robert CERVANTES, Andrew CELAYA
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Patent number: 11710686Abstract: Methods of forming semiconductor packages include providing a lead frame having leads and no tie-bars. Tape is attached to the lead frame and one or more semiconductor die are coupled therewith. Electrical contacts of the die are interconnected with the leads using electrical connectors. An encapsulated assembly is formed by at least partially encapsulating the die and electrical connectors. The assembly is singulated to form a semiconductor package. The tape is detached from the package or encapsulated assembly. One or more die attach flags may be attached to the tape and the die may be attached thereto. Semiconductor packages formed using the methods include one or more semiconductor die at least partially encapsulated, pins exposed through the encapsulant, electrical connectors within the encapsulant and electrically interconnecting the pins with electrical contacts of the die, and no tie-bars coupling the die with the pins. Packages may also include die attach flags.Type: GrantFiled: December 1, 2021Date of Patent: July 25, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Stephen St. Germain, Jay A. Yoder, Dennis Lee Conner, Frank Robert Cervantes, Andrew Celaya
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Publication number: 20220084920Abstract: Methods of forming semiconductor packages include providing a lead frame having leads and no tie-bars. Tape is attached to the lead frame and one or more semiconductor die are coupled therewith. Electrical contacts of the die are interconnected with the leads using electrical connectors. An encapsulated assembly is formed by at least partially encapsulating the die and electrical connectors. The assembly is singulated to form a semiconductor package. The tape is detached from the package or encapsulated assembly. One or more die attach flags may be attached to the tape and the die may be attached thereto. Semiconductor packages formed using the methods include one or more semiconductor die at least partially encapsulated, pins exposed through the encapsulant, electrical connectors within the encapsulant and electrically interconnecting the pins with electrical contacts of the die, and no tie-bars coupling the die with the pins. Packages may also include die attach flags.Type: ApplicationFiled: December 1, 2021Publication date: March 17, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Stephen ST. GERMAIN, Jay A. YODER, Dennis Lee CONNER, Frank Robert CERVANTES, Andrew Celaya
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Patent number: 11239602Abstract: A method of assembling an electronic control unit comprises assembling a printed circuit board (PCB) substrate with a terminal carrier holding a plurality of terminal pins comprising a right angle bend into a housing using a rotational motion. The terminal carrier generally extends perpendicularly from the PCB substrate. A first end of each of the plurality of terminal pins is inserted into the PCB substrate and a second end of each of the plurality of terminal pins extends through the terminal carrier. The second ends of the plurality of terminal pins generally extend into one or more connector openings in one of four sides of the housing and the terminal carrier interlocks with the housing to hold the PCB substrate with the terminal carrier and the plurality of terminal pins in place.Type: GrantFiled: December 18, 2019Date of Patent: February 1, 2022Assignee: VEONEER US INC.Inventor: Jacob Jay Yoder
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Patent number: 11217515Abstract: Methods of forming semiconductor packages include providing a lead frame having leads and no tie-bars. Tape is attached to the lead frame and one or more semiconductor die are coupled therewith. Electrical contacts of the die are interconnected with the leads using electrical connectors. An encapsulated assembly is formed by at least partially encapsulating the die and electrical connectors. The assembly is singulated to form a semiconductor package. The tape is detached from the package or encapsulated assembly. One or more die attach flags may be attached to the tape and the die may be attached thereto. Semiconductor packages formed using the methods include one or more semiconductor die at least partially encapsulated, pins exposed through the encapsulant, electrical connectors within the encapsulant and electrically interconnecting the pins with electrical contacts of the die, and no tie-bars coupling the die with the pins. Packages may also include die attach flags.Type: GrantFiled: August 29, 2019Date of Patent: January 4, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Stephen St. Germain, Jay A. Yoder, Dennis Lee Conner, Frank Robert Cervantes, Andrew Celaya
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Publication number: 20210194176Abstract: A method of assembling an electronic control unit comprises assembling a printed circuit board (PCB) substrate with a terminal carrier holding a plurality of terminal pins comprising a right angle bend into a housing using a rotational motion. The terminal carrier generally extends perpendicularly from the PCB substrate. A first end of each of the plurality of terminal pins is inserted into the PCB substrate and a second end of each of the plurality of terminal pins extends through the terminal carrier. The second ends of the plurality of terminal pins generally extend into one or more connector openings in one of four sides of the housing and the terminal carrier interlocks with the housing to hold the PCB substrate with the terminal carrier and the plurality of terminal pins in place.Type: ApplicationFiled: December 18, 2019Publication date: June 24, 2021Inventor: Jacob Jay Yoder
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Patent number: 10834833Abstract: A method of assembling an electronic control unit comprises assembling a terminal carrier holding a plurality of terminal pins into a housing using translational motions, inserting at least one comb tool through one or more connector openings until a plurality of beams of the comb tool are placed between the terminal carrier, a comb support feature, and a shoulder on an end of each of a plurality of terminal pins, and assembling a printed circuit board substrate to the plurality of terminal pins by inserting the end of each of the plurality of terminal pins into the printed circuit board substrate using a press fit.Type: GrantFiled: December 18, 2019Date of Patent: November 10, 2020Assignee: VEONEER US INC.Inventor: Jacob Jay Yoder
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Patent number: 10785881Abstract: An apparatus includes a housing, a circuit board, a sealant and a baseplate. The housing may have a shelf and a flange along an open side. The circuit board may be (i) disposed on the shelf of the housing and inside the flange of the housing and (ii) secured to the housing. The sealant may be dispensed (i) through the open side of the housing and (ii) along a gap between the flange and the circuit board. The baseplate may be compressed to the housing thereby causing the sealant to flow between (i) the baseplate and the circuit board and (ii) the baseplate and the flange.Type: GrantFiled: January 22, 2019Date of Patent: September 22, 2020Assignee: VEONEER US INC.Inventors: Demetri Stilianos, Jacob Jay Yoder, Luis Fernando Sanchez, Floyd J. Malecke
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Publication number: 20200236797Abstract: An apparatus includes a housing, a circuit board, a sealant and a baseplate. The housing may have a shelf and a flange along an open side. The circuit board may be (i) disposed on the shelf of the housing and inside the flange of the housing and (ii) secured to the housing. The sealant may be dispensed (i) through the open side of the housing and (ii) along a gap between the flange and the circuit board. The baseplate may be compressed to the housing thereby causing the sealant to flow between (i) the baseplate and the circuit board and (ii) the baseplate and the flange.Type: ApplicationFiled: January 22, 2019Publication date: July 23, 2020Inventors: Demetri Stilianos, Jacob Jay Yoder, Luis Fernando Sanchez, Floyd J. Malecke
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Patent number: 10522448Abstract: Implementations of a semiconductor device package may include: a plurality of electrical contacts on a first face of a die, at least one clip electrically and mechanically coupled with at least one electrical contact on a second face of the die where the second face of the die is on an opposing side of the die from the first face of the die. The at least one clip may include at least one lead in electrical communication with the at least one electrical contact on the second face of the die. A mold compound or an encapsulating compound may be included around the die and a majority of the at least one clip where a portion of the at least one lead and a portion of the plurality of electrical contacts on the first face of the die are not overmolded or encapsulated. The semiconductor package includes no lead frame.Type: GrantFiled: December 6, 2017Date of Patent: December 31, 2019Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Stephen St. Germain, Roger M. Arbuthnot, Jay A. Yoder, Dennis Lee Conner
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Publication number: 20190385939Abstract: Methods of forming semiconductor packages include providing a lead frame having leads and no tie-bars. Tape is attached to the lead frame and one or more semiconductor die are coupled therewith. Electrical contacts of the die are interconnected with the leads using electrical connectors. An encapsulated assembly is formed by at least partially encapsulating the die and electrical connectors. The assembly is singulated to form a semiconductor package. The tape is detached from the package or encapsulated assembly. One or more die attach flags may be attached to the tape and the die may be attached thereto. Semiconductor packages formed using the methods include one or more semiconductor die at least partially encapsulated, pins exposed through the encapsulant, electrical connectors within the encapsulant and electrically interconnecting the pins with electrical contacts of the die, and no tie-bars coupling the die with the pins. Packages may also include die attach flags.Type: ApplicationFiled: August 29, 2019Publication date: December 19, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Stephen ST. GERMAIN, Jay A. YODER, Dennis Lee CONNER, Frank Robert CERVANTES, Andrew Celaya
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Publication number: 20180096925Abstract: Implementations of a semiconductor device package may include: a plurality of electrical contacts on a first face of a die, at least one clip electrically and mechanically coupled with at least one electrical contact on a second face of the die where the second face of the die is on an opposing side of the die from the first face of the die. The at least one clip may include at least one lead in electrical communication with the at least one electrical contact on the second face of the die. A mold compound or an encapsulating compound may be included around the die and a majority of the at least one clip where a portion of the at least one lead and a portion of the plurality of electrical contacts on the first face of the die are not overmolded or encapsulated. The semiconductor package includes no lead frame.Type: ApplicationFiled: December 6, 2017Publication date: April 5, 2018Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Stephen St. Germain, Roger M. Arbuthnot, Jay A. Yoder, Dennis Lee Conner
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Patent number: 9911684Abstract: A system, in some embodiments, comprises: a first surface of a lead frame; a second surface of the lead frame, opposite the first surface, said second surface having been etched; and one or more holes passing through said lead frame and coincident with the first and second surfaces, wherein said one or more holes are adapted to control fluid flow on said first surface.Type: GrantFiled: August 18, 2016Date of Patent: March 6, 2018Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Stephen St. Germain, Dennis Lee Conner, Jay A. Yoder
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Publication number: 20180053712Abstract: A system, in some embodiments, comprises: a first surface of a lead frame; a second surface of the lead frame, opposite the first surface, said second surface having been etched; and one or more holes passing through said lead frame and coincident with the first and second surfaces, wherein said one or more holes are adapted to control fluid flow on said first surface.Type: ApplicationFiled: August 18, 2016Publication date: February 22, 2018Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Stephen ST. GERMAIN, Dennis Lee CONNER, Jay A. YODER
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Patent number: 9870986Abstract: Implementations of a semiconductor device package may include: a plurality of electrical contacts on a first face of a die, at least one clip electrically and mechanically coupled with at least one electrical contact on a second face of the die where the second face of the die is on an opposing side of the die from the first face of the die. The at least one clip may include at least one lead in electrical communication with the at least one electrical contact on the second face of the die. A mold compound or an encapsulating compound may be included around the die and a majority of the at least one clip where a portion of the at least one lead and a portion of the plurality of electrical contacts on the first face of the die are not overmolded or encapsulated. The semiconductor package includes no lead frame.Type: GrantFiled: December 28, 2016Date of Patent: January 16, 2018Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Stephen St. Germain, Roger M. Arbuthnot, Jay A. Yoder, Dennis Lee Conner
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Patent number: 9847219Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a layer of material by placing the semiconductor wafer onto a carrier tape with the layer of material adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the layer of material within the singulation lines, and separating portions of the layer of material using a fluid.Type: GrantFiled: September 16, 2016Date of Patent: December 19, 2017Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: William F. Burghout, Dennis Lee Conner, Michael J. Seddon, Jay A. Yoder, Gordon M. Grivna
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Publication number: 20170110391Abstract: Implementations of a semiconductor device package may include: a plurality of electrical contacts on a first face of a die, at least one clip electrically and mechanically coupled with at least one electrical contact on a second face of the die where the second face of the die is on an opposing side of the die from the first face of the die. The at least one clip may include at least one lead in electrical communication with the at least one electrical contact on the second face of the die. A mold compound or an encapsulating compound may be included around the die and a majority of the at least one clip where a portion of the at least one lead and a portion of the plurality of electrical contacts on the first face of the die are not overmolded or encapsulated. The semiconductor package includes no lead frame.Type: ApplicationFiled: December 28, 2016Publication date: April 20, 2017Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Stephen ST. GERMAIN, Roger M. ARBUTHNOT, Jay A. YODER, Dennis Lee CONNER
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Patent number: 9558968Abstract: A method of forming a semiconductor device package. Implementations may include providing an adhesive tape; contacting at least one electrical contact of at least one die with an adhesive surface of the adhesive tape; mechanically and electrically coupling at least one clip with the at least one die and contacting an electrical contact of the at least one clip with the adhesive surface; one of overmolding and encapsulating the at least one die and a majority of the at least one clip with one of a mold compound and an encapsulating compound, respectively, wherein the at least one electrical contact of the at least one die and the electrical contact of the at least one clip are not one of overmolded and encapsulated, forming the semiconductor device package; removing the semiconductor device package from the adhesive surface; and including no leadframe in the package.Type: GrantFiled: September 11, 2014Date of Patent: January 31, 2017Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Stephen St. Germain, Roger M. Arbuthnot, Jay A. Yoder, Dennis Lee Conner
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Publication number: 20170004965Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a layer of material by placing the semiconductor wafer onto a carrier tape with the layer of material adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the layer of material within the singulation lines, and separating portions of the layer of material using a fluid.Type: ApplicationFiled: September 16, 2016Publication date: January 5, 2017Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: William F. BURGHOUT, Dennis Lee CONNER, Michael J. SEDDON, Jay A. YODER, Gordon M. GRIVNA