Abstract: In a digital computer system which employs a plurality of host processors, at least two system buses and a plurality of peripheral input/output ports, an input/output system is provided whereby ownership of the input/output channels is shared. The device controller employs a first port controller having a first ownership latch, a second port controller having a second ownership latch, a first bus, a dedicated microprocessor having control over the first bus (the MPU bus), a second, higher-speed bus, a multiple-channel direct memory access (DMA) controller which is a state machine which controls the second bus (the data buffer bus), a bus switch for exchanging data between buses, a multiple device peripheral device interface, namely a Small Computer System Interface (SCSI), and at least provision for interface with data communication equipment (DCEs) or data terminal equipment (DTEs).

Abstract: An electrical keying system for a set of incompatible module pairs to prevent powerup of an electrically incompatible module pair in a set.

Abstract: A fault tolerant/failsafe current limit system for shutting down a power supply if an overcurrent condition exists at one or more selected load circuits in a set of load circuits. A current limit circuit couples each selected load circuit to the power supply and includes at least two monitoring circuits for detecting whether the current delivered to the selected load circuit exceeds a preselected limit. The power supply will be shut down unless both monitor circuits agree that the delivered current does not exceed the preselected limit.