Patents by Inventor Jay Ackerman

Jay Ackerman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12092664
    Abstract: One or more layout techniques may be used to balance a current sense circuit. The current sense circuit may include upstairs resistors for an amplifier which are formed of polysilicon material. The upstairs resistors may be arranged symmetrically about one or more stress gradients for improving an accuracy of the current sense circuit. The stress gradients may include stress gradients about an axis and stress gradients from a die edge.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: September 17, 2024
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Ryan Desrosiers, Jay Ackerman, Mark Rutherford
  • Patent number: 12040758
    Abstract: An integrated circuit for measuring current while receiving wireless power is described. The integrated circuit measures a current across a resistor by an amplifier. A gain of the amplifier is based on a pair of matched upstairs resistors and a pair of matched downstairs resistors. The pair of matched upstairs resistors may include an offset in resistance. The integrated circuit includes a switch matrix with switches coupled between the integrated resistor and the pair of matched upstairs resistors. The offset for the pair of matched upstairs resistors may be measured by selectively controlling the switches.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: July 16, 2024
    Assignee: Avago Technologies International Sales Pte, Limited
    Inventors: Ryan Desrosiers, Jay Ackerman, Mark Rutherford
  • Publication number: 20240003943
    Abstract: One or more layout techniques may be used to balance a current sense circuit. The current sense circuit may include upstairs resistors for an amplifier which are formed of polysilicon material. The upstairs resistors may be arranged symmetrically about one or more stress gradients for improving an accuracy of the current sense circuit. The stress gradients may include stress gradients about an axis and stress gradients from a die edge.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 4, 2024
    Inventors: Ryan Desrosiers, Jay Ackerman, Mark Rutherford
  • Publication number: 20240003941
    Abstract: A structure is described which includes two amplifiers in parallel. A first amplifier is considered an always-on amplifier. The always on amplifier provides continual measurements of a current (Isns) across an integrated polysilicon resistor for one or more analog control loops. A second amplifier is considered a switched amplifier. The switched amplifier provides measurements of the current (Isns) for one or more digital control loops. The switched amplifier is switched by one or more switches for performing offset measurements with high accuracy.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 4, 2024
    Inventors: Ryan Desrosiers, Jay Ackerman, Mark Rutherford
  • Publication number: 20240007063
    Abstract: An integrated circuit for measuring current while receiving wireless power is described. The integrated circuit measures a current across a resistor by an amplifier. A gain of the amplifier is based on a pair of matched upstairs resistors and a pair of matched downstairs resistors. The pair of matched upstairs resistors may include an offset in resistance. The integrated circuit includes a switch matrix with switches coupled between the integrated resistor and the pair of matched upstairs resistors. The offset for the pair of matched upstairs resistors may be measured by selectively controlling the switches.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 4, 2024
    Inventors: Ryan Desrosiers, Jay Ackerman, Mark Rutherford
  • Patent number: 11018581
    Abstract: A converter includes a first circuit. The first circuit includes a first input that receives a power supply signal, a second input that receives a first signal, and a first output that outputs a second signal having an amplitude that is based on a frequency of the first signal. The first signal is based on an error value and a third signal, and the third signal is independent of feedback of the first circuit. The converter also includes a second circuit having a second output coupled to the second input and that outputs the third signal. The second circuit nonlinearly adapts the third signal based on the power supply signal and a reference signal.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: May 25, 2021
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Yongjie Jiang, Kevin Vannorsdel, Jay Ackerman
  • Publication number: 20190305679
    Abstract: A converter includes a first circuit. The first circuit includes a first input that receives a power supply signal, a second input that receives a first signal, and a first output that outputs a second signal having an amplitude that is based on a frequency of the first signal. The first signal is based on an error value and a third signal, and the third signal is independent of feedback of the first circuit. The converter also includes a second circuit having a second output coupled to the second input and that outputs the third signal. The second circuit nonlinearly adapts the third signal based on the power supply signal and a reference signal.
    Type: Application
    Filed: March 29, 2018
    Publication date: October 3, 2019
    Inventors: Yongjie Jiang, Kevin Vannorsdel, Jay Ackerman
  • Publication number: 20160204702
    Abstract: A hysteretic switching regulator with low output ripple voltage is disclosed herein. A detector and controller is specifically used to adjust a parameter of the hysteretic switching regulator to compensate for changes in one or more of input voltage and desired output voltage to maintain the output ripple voltage within some desired range.
    Type: Application
    Filed: March 6, 2015
    Publication date: July 14, 2016
    Applicant: Broadcom Corporation
    Inventors: Aravind Kumar PADYANA, Iuri Mehr, Jay Ackerman, Mark Rutherford, Daniel Melendy, Eric Martin Hayes
  • Patent number: 6404241
    Abstract: A current-mode peak detector circuit is disclosed. The current-mode peak detector circuit includes an input transistor for receiving an input current that impresses a voltage on a control node, a pair of transistors for providing an output current in response to the voltage at the control node, and a decay control circuit for controlling the decay of the voltage at the control node such that the output current is representative of a peak value of the input current signal. A clamp circuit may be provided for clamping the input voltage to a predetermined level. All of the elements of the current-mode peak detector circuit may be realized using transistors for facilitating integration of the current-mode peak detector circuit on an integrated circuit. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other researcher to quickly ascertain the subject matter of the technical disclosure.
    Type: Grant
    Filed: January 13, 2000
    Date of Patent: June 11, 2002
    Assignee: LSI Logic Corporation
    Inventor: Jay Ackerman