Patents by Inventor Jay Ashjaee

Jay Ashjaee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10829864
    Abstract: This disclosure enables high-productivity controlled fabrication of uniform porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: November 10, 2020
    Assignee: TruTag Technologies, Inc.
    Inventors: Karl-Josef Kramer, Mehrdad M. Moslehi, Subramanian Tamilmani, George Kamian, Jay Ashjaee, Takao Yonehara
  • Publication number: 20180347063
    Abstract: This disclosure enables high-productivity controlled fabrication of uniform porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.
    Type: Application
    Filed: December 21, 2017
    Publication date: December 6, 2018
    Inventors: Karl-Josef Kramer, Mehrdad M. Moslehi, Subramanian Tamilmani, George Kamian, Jay Ashjaee, Takao Yonehara
  • Patent number: 10138565
    Abstract: This disclosure enables high-productivity fabrication of porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: November 27, 2018
    Assignee: TruTag Technologies, Inc.
    Inventors: Takao Yonehara, Subramanian Tamilmani, Karl-Josef Kramer, Jay Ashjaee, Mehrdad M. Moslehi, Yasuyoshi Miyaji, Noriyuki Hayashi, Takamitsu Inahara
  • Publication number: 20180323087
    Abstract: This disclosure enables high-productivity fabrication of porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.
    Type: Application
    Filed: January 4, 2017
    Publication date: November 8, 2018
    Inventors: Takao Yonehara, Subramanian Tamilmani, Karl-Josef Kramer, Jay Ashjaee, Mehrdad M. Moslehi, Yasuyoshi Miyaji, Noriyuki Hayashi, Takamitsu Inahara
  • Patent number: 9890465
    Abstract: This disclosure enables high-productivity controlled fabrication of uniform porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: February 13, 2018
    Assignee: TruTag Technologies, Inc.
    Inventors: Karl-Josef Kramer, Mehrdad M. Moslehi, Subramanian Tamilmani, George D. Kamian, Jay Ashjaee, Takao Yonehara
  • Patent number: 9870937
    Abstract: High productivity thin film deposition methods and tools are provided wherein a thin film semiconductor material layer with a thickness in the range of less than 1 micron to 100 microns is deposited on a plurality of wafers in a reactor. The wafers are loaded on a batch susceptor and the batch susceptor is positioned in the reactor such that a tapered gas flow space is created between the susceptor and an interior wall of the reactor. Reactant gas is then directed into the tapered gas space and over each wafer thereby improving deposition uniformity across each wafer and from wafer to wafer.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: January 16, 2018
    Assignee: OB Realty, LLC
    Inventors: Mehrdad M. Moslehi, Karl-Josef Kramer, Jay Ashjaee, George D. Kamian, David Mordo, Takao Yonehara
  • Patent number: 9771662
    Abstract: This disclosure enables high-productivity fabrication of porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: September 26, 2017
    Assignee: OB REALTY, LLC
    Inventors: Takao Yonehara, Subramanian Tamilmani, Karl-Josef Kramer, Jay Ashjaee, Mehrdad M. Moslehi, Yasuyoshi Miyaji, Noriyuki Hayashi, Takamitsu Inahara
  • Publication number: 20170243767
    Abstract: This disclosure enables high-productivity fabrication of porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.
    Type: Application
    Filed: January 4, 2017
    Publication date: August 24, 2017
    Inventors: Takao Yonehara, Subramanian Tamilmani, Karl-Josef Kramer, Jay Ashjaee, Mehrdad M. Moslehi, Yasuyoshi Miyaji, Noriyuki Hayashi, Takamitsu Inahara
  • Publication number: 20170236954
    Abstract: Fabrication methods and structures relating to multi-level metallization for solar cells as well as fabrication methods and structures for forming back contact solar cells are provided.
    Type: Application
    Filed: April 3, 2017
    Publication date: August 17, 2017
    Inventors: Karl-Josef Kramer, Mehrdad M. Moslehi, Pawan Kapur, Virendra V. Rana, David Dutton, Sean M. Seutter, Anthony Calcaterra, Jay Ashjaee, Takao Yonehara
  • Patent number: 9401276
    Abstract: An apparatus for forming porous silicon layers on at least two surfaces of a plurality of silicon templates in a batch electrochemical anodic etch process is provided. The apparatus comprises a plurality of edge-sealing template mounts operable to prevent formation of porous silicon at the edges of a plurality of templates. An electrolyte is disposed among the plurality of templates. The apparatus further comprises a power supply operable to switch polarity, change current intensity, and control etching time to produce the porous silicon layers.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: July 26, 2016
    Assignee: Solexel, Inc.
    Inventors: Mehrdad M. Moslehi, Karl-Josef Kramer, David Xuan-Qi Wang, Pawan Kapur, Somnath Nag, George D. Kamian, Jay Ashjaee, Takao Yonehara
  • Publication number: 20160186358
    Abstract: This disclosure enables high-productivity fabrication of porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.
    Type: Application
    Filed: July 6, 2015
    Publication date: June 30, 2016
    Inventors: Takao Yonehara, Subramanian Tamilmani, Karl-Josef Kramer, Jay Ashjaee, Mehrdad M. Moslehi, Yasuyoshi Miyaji, Noriyuki Hayashi, Takamitsu Inahara
  • Patent number: 9337374
    Abstract: Processing equipment for the metallization of a plurality of semiconductor workpieces. A controlled atmospheric non-oxidizing gas region comprises at least two enclosed deposition zones, the controlled atmospheric non-oxidizing gas region is isolated from external oxidizing ambient. A temperature controller adjusts the temperature of the semiconductor workpiece in each of the at least two enclosed deposition zones. Each of the enclosed deposition zones comprising at least one spray gun for the metallization of the semiconductor workpiece. A transport system moves the semiconductor workpiece through the controlled atmospheric non-oxidizing gas region. A batch carrier plate carries the semiconductor workpiece through the controlled atmospheric non-oxidizing gas region. The controlled atmospheric non-oxidizing gas region further comprises a gas-based pre-cleaning zone.
    Type: Grant
    Filed: December 23, 2012
    Date of Patent: May 10, 2016
    Assignee: Solexel, Inc.
    Inventors: Karl-Josef Kramer, Jay Ashjaee, Mehrdad M. Moslehi, Anthony Calcaterra, David Dutton, Pawan Kapur, Sean Seutter, Homi Fatemi
  • Publication number: 20150207002
    Abstract: Solar cell array solutions including monolithic solar cell arrays and fabrication methods. A first patterned cell metallization contacts base and emitter regions of each of a plurality of solar cells having a light receiving frontside and a backside. An electrically insulating continuous backplane layer is attached to the backside of the solar cells and covers the first cell metallization of each of the solar cells. Via holes through the continuous backplane layer provide access to the first cell metallization. A second cell metallization is connected to the first cell metallization of each of the solar cells and electrically interconnects the solar cells in the array.
    Type: Application
    Filed: September 2, 2014
    Publication date: July 23, 2015
    Inventors: Mehrdad M. Moslehi, Thom Stalcup, Michael Wingert, Jay Ashjaee, Pawan Kapur, Homi Fatemi
  • Patent number: 9076642
    Abstract: This disclosure enables high-productivity fabrication of porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.
    Type: Grant
    Filed: September 24, 2011
    Date of Patent: July 7, 2015
    Assignee: Solexel, Inc.
    Inventors: Takao Yonehara, Subramanian Tamilmani, Karl-Josef Kramer, Jay Ashjaee, Mehrdad M. Moslehi, Yasuyoshi Miyaji, Noriyuki Hayashi, Takamitsu Inahara
  • Publication number: 20150159292
    Abstract: This disclosure enables high-productivity controlled fabrication of uniform porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.
    Type: Application
    Filed: December 8, 2014
    Publication date: June 11, 2015
    Applicant: Solexel, Inc.
    Inventors: Karl-Josef Kramer, Mehrdad M. Moslehi, Subramanian Tamilmani, George D. Kamian, Jay Ashjaee, Takao Yonehara
  • Patent number: 8906218
    Abstract: This disclosure enables high-productivity controlled fabrication of uniform porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: December 9, 2014
    Assignee: Solexel, Inc.
    Inventors: Karl-Josef Kramer, Mehrdad M. Moslehi, Subramanian Tamilmani, George Kamian, Jay Ashjaee, Takao Yonehara
  • Publication number: 20130180847
    Abstract: This disclosure enables high-productivity fabrication of porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.
    Type: Application
    Filed: September 24, 2011
    Publication date: July 18, 2013
    Inventors: Takao Yonehara, Subramanian Tamilmani, Karl-Josef Kramer, Jay Ashjaee, Mehrdad M. Moslehi, Yasuyoshi Miyaji, Noriyuki Hayashi, Takamitsu Inahara
  • Publication number: 20130171808
    Abstract: This disclosure presents manufacturing methods and apparatus designs for making TFSSs from both sides of a re-usable semiconductor template, thus effectively increasing the substrate manufacturing throughput and reducing the substrate manufacturing cost. This approach also reduces the amortized starting template cost per manufactured substrate (TFSS) by about a factor of 2 for a given number of template reuse cycles.
    Type: Application
    Filed: July 20, 2012
    Publication date: July 4, 2013
    Applicant: SOLEXEL, INC.
    Inventors: Mehrdad M. Moslehi, Karl-Josef Kramer, David Xuan-Qi Wang, Pawan Kapur, Somnath Nag, George D. Kamian, Jay Ashjaee, Takao Yonehara
  • Patent number: 8241940
    Abstract: This disclosure presents manufacturing methods and apparatus designs for making TFSSs from both sides of a re-usable semiconductor template, thus effectively increasing the substrate manufacturing throughput and reducing the substrate manufacturing cost. This approach also reduces the amortized starting template cost per manufactured substrate (TFSS) by about a factor of 2 for a given number of template reuse cycles.
    Type: Grant
    Filed: February 12, 2011
    Date of Patent: August 14, 2012
    Assignee: Solexel, Inc.
    Inventors: Mehrdad M. Moslehi, Karl-Josef Kramer, David Xuan-Qi Wang, Pawan Kapur, Somnath Nag, George D Kamian, Jay Ashjaee, Takao Yonehara
  • Publication number: 20120192789
    Abstract: This disclosure enables gas recovery and utilization for use in deposition systems and processes. The system includes a thin-film semiconductor layer deposition system comprising a deposition reactor, precursor gas feeds, and a gas recovery system.
    Type: Application
    Filed: December 31, 2011
    Publication date: August 2, 2012
    Applicant: SOLEXEL, INC.
    Inventors: Karl-Josef Kramer, Mehrdad M. Moslehi, Seiichi Yokoi, George D. Kamian, Shashank Sharma, Jay Ashjaee