Patents by Inventor Jay Chang

Jay Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11532730
    Abstract: Stress memorization techniques (SMTs) for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a capping layer over a fin structure; forming an amorphous region within the fin structure while the capping layer is disposed over the fin structure; and performing an annealing process to recrystallize the amorphous region. The capping layer enables the fin structure to retain stress effects induced by forming the amorphous region and/or performing the annealing process.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Cheng Lo, Sun-Jay Chang
  • Publication number: 20220359648
    Abstract: A circuit device includes core circuitry. The circuit device further includes a first plurality of guard rings having a first dopant type, wherein the first plurality of guard rings is around a periphery of the core circuitry. The circuit device further includes a second plurality of guard rings having a second dopant type, wherein the second dopant type is opposite to the first dopant type, and at least one guard ring of the second plurality of guard rings is around a periphery of at least one guard ring of the first plurality of guard rings.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: Wan-Yen LIN, Wun-Jie LIN, Yu-Ti SU, Bo-Ting CHEN, Jen-Chou TSENG, Kuo-Ji CHEN, Sun-Jay CHANG, Min-Chang LIANG
  • Patent number: 11450735
    Abstract: A method includes implanting a first guard ring around a periphery of core circuitry. The implanting of the first guard ring includes implanting a first component a first distance from the core circuitry on a first side of the core circuitry, and implanting a second component a second distance from the core circuitry on a second side of the core circuitry, wherein the second distance is greater than the first distance. The method further includes implanting a second guard ring around the periphery of the core circuitry. The implanting of the second guard ring includes implanting a third component a third distance from the core circuitry on the first side of the core circuitry, and implanting a fourth component a fourth distance from the core circuitry on the second side of the core circuitry, wherein the third distance is greater than the fourth distance.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: September 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wan-Yen Lin, Wun-Jie Lin, Yu-Ti Su, Bo-Ting Chen, Jen-Chou Tseng, Kuo-Ji Chen, Sun-Jay Chang, Min-Chang Liang
  • Publication number: 20220023381
    Abstract: The present invention relates to a method for treating diseases associated with type-1 interferon signaling. Particularly, the present invention is directed to use of specific inhibitors of Voltage-Dependent Anion Channel (VDAC1), such as piperazine- and/or piperidine-derivatives, among others, e.g., peptides and oligonucleotides, for treating an autoimmune disease.
    Type: Application
    Filed: November 26, 2019
    Publication date: January 27, 2022
    Inventors: Varda SHOSHAN-BARMATZ, Jay CHANG, Jeonghan KIM
  • Publication number: 20210091176
    Abstract: A method includes implanting a first guard ring around a periphery of core circuitry. The implanting of the first guard ring includes implanting a first component a first distance from the core circuitry on a first side of the core circuitry, and implanting a second component a second distance from the core circuitry on a second side of the core circuitry, wherein the second distance is greater than the first distance. The method further includes implanting a second guard ring around the periphery of the core circuitry. The implanting of the second guard ring includes implanting a third component a third distance from the core circuitry on the first side of the core circuitry, and implanting a fourth component a fourth distance from the core circuitry on the second side of the core circuitry, wherein the third distance is greater than the fourth distance.
    Type: Application
    Filed: November 19, 2020
    Publication date: March 25, 2021
    Inventors: Wan-Yen LIN, Wun-Jie LIN, Yu-Ti SU, Bo-Ting CHEN, Jen-Chou TSENG, Kuo-Ji CHEN, Sun-Jay CHANG, Min-Chang LIANG
  • Patent number: 10868112
    Abstract: A circuit device includes core circuitry. The circuit device further includes a guard ring surrounding the core circuitry. The guard ring includes a first plurality of fin structures arranged in a first direction parallel to a first side of the core circuitry, wherein adjacent fin structures of the first plurality of fin structures are separated by a first distance. The guard ring further includes a second plurality of fin structures arranged in a second direction parallel to a second side of the core circuitry, wherein adjacent fin structures of the second plurality of fin structures are separated by a second distance, and the second distance is smaller than the first distance.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wan-Yen Lin, Wun-Jie Lin, Yu-Ti Su, Bo-Ting Chen, Jen-Chou Tseng, Kuo-Ji Chen, Sun-Jay Chang, Min-Chang Liang
  • Publication number: 20200357900
    Abstract: Stress memorization techniques (SMTs) for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a capping layer over a fin structure; forming an amorphous region within the fin structure while the capping layer is disposed over the fin structure; and performing an annealing process to recrystallize the amorphous region. The capping layer enables the fin structure to retain stress effects induced by forming the amorphous region and/or performing the annealing process.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Inventors: Wen-Cheng Lo, Sun-Jay Chang
  • Patent number: 10727319
    Abstract: Stress memorization techniques (SMTs) for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a capping layer over a fin structure; forming an amorphous region within the fin structure while the capping layer is disposed over the fin structure; and performing an annealing process to recrystallize the amorphous region. The capping layer enables the fin structure to retain stress effects induced by forming the amorphous region and/or performing the annealing process.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Wen-Cheng Lo, Sun-Jay Chang
  • Patent number: 10349638
    Abstract: A non-human transgenic animal that contains in its genome a nucleic acid encoding human ARCAP operably linked to a liver-specific promoter. The transgenic animal expresses the human ARCAP protein and develops tumors of the liver, spleen, abdomen, or lymph. Also provided is a cell line derived from the non-human transgenic animal expressing the human ARCAP gene. Further provided is a method for producing a transgenic mouse by micro-injecting into a fertilized mouse oocyte a vector that contains a human ARCAP cDNA operably linked to a liver-specific promoter and transferring the micro-injected mouse oocyte into a foster mouse.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: July 16, 2019
    Inventor: Tai-Jay Chang
  • Patent number: 10269986
    Abstract: A diode includes a first plurality of combo fins having lengthwise directions parallel to a first direction, wherein the first plurality of combo fins comprises portions of a first conductivity type. The diodes further includes a second plurality of combo fins having lengthwise directions parallel to the first direction, wherein the second plurality of combo fins includes portions of a second conductivity type opposite the first conductivity type. An isolation region is located between the first plurality of combo fins and the second plurality of combo fins. The first and the second plurality of combo fins form a cathode and an anode of the diode. The diode is configured to have a current flowing in a second direction perpendicular to the first direction, with the current flowing between the anode and the cathode.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sun-Jay Chang, Ming-Hsiang Song, Jen-Chou Tseng, Wun-Jie Lin, Bo-Ting Chen
  • Publication number: 20190096990
    Abstract: A circuit device includes core circuitry. The circuit device further includes a guard ring surrounding the core circuitry. The guard ring includes a first plurality of fin structures arranged in a first direction parallel to a first side of the core circuitry, wherein adjacent fin structures of the first plurality of fin structures are separated by a first distance. The guard ring further includes a second plurality of fin structures arranged in a second direction parallel to a second side of the core circuitry, wherein adjacent fin structures of the second plurality of fin structures are separated by a second distance, and the second distance is smaller than the first distance.
    Type: Application
    Filed: November 9, 2018
    Publication date: March 28, 2019
    Inventors: Wan-Yen LIN, Wun-Jie LIN, Yu-Ti SU, Bo-Ting CHEN, Jen-Chou TSENG, Kuo-Ji CHEN, Sun-Jay CHANG, Min-Chang LIANG
  • Publication number: 20190014756
    Abstract: A non-human transgenic animal that contains in its genome a nucleic acid encoding human ARCAP operably linked to a liver-specific promoter. The transgenic animal expresses the human ARCAP protein and develops tumors of the liver, spleen, abdomen, or lymph. Also provided is a cell line derived from the non-human transgenic animal expressing the human ARCAP gene. Further provided is a method for producing a transgenic mouse by micro-injecting into a fertilized mouse oocyte a vector that contains a human ARCAP cDNA operably linked to a liver-specific promoter and transferring the micro-injected mouse oocyte into a foster mouse.
    Type: Application
    Filed: July 14, 2017
    Publication date: January 17, 2019
    Inventor: Tai-Jay Chang
  • Patent number: 10128329
    Abstract: A method of making a circuit device includes forming core circuitry. The core circuitry includes a doped region in the core circuit. The method further includes implanting a first set of guard rings around a periphery of the core circuitry. The first set of guard rings has a first dopant type. Implanting the first set of guard rings includes implanting the first set of guard rings spaced from the doped region. The method further includes implanting a second set of guard rings having a second dopant type, wherein the second dopant type being opposite to the first dopant type. At least one guard ring of the second set of guard rings is around a periphery of at least one guard ring of the first set of guard rings.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: November 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wan-Yen Lin, Wun-Jie Lin, Yu-Ti Su, Bo-Ting Chen, Jen-Chou Tseng, Kuo-Ji Chen, Sun-Jay Chang, Min-Chang Liang
  • Patent number: 9984153
    Abstract: A music play method includes detecting at least one group of dynamic parameters of an electronic device and obtaining detected dynamic parameters. Once a music playlist of the electronic device is determined to be adjusted according to the detected dynamic parameters, the music play is adjusted according to the detected dynamic parameters and an adjusted music playlist is obtained.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: May 29, 2018
    Assignee: Chiun Mai Communication Systems, Inc.
    Inventors: Chih-Pu Hsu, Hsiu-Hua Yen, Sung-Jay Chang
  • Patent number: 9865592
    Abstract: A semiconductor structure comprises a semiconductor substrate and a shallow trench isolation (STI) feature over the substrate. The STI feature includes first and second portions. A top surface of the first portion is lower than a top surface of the second portion. The semiconductor structure further comprises fin active regions; conductive features on the fin active regions and the STI feature; and dielectric features separating the conductive features from the fin active regions. The semiconductor structure further comprises a first gate stack having a first one of the dielectric features and a first one of the conductive features overlying the first one of the dielectric features; and a second gate stack having a second one of the dielectric features and a second one of the conductive features overlying the second one of the dielectric features.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: January 9, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Hsin Hu, Sun-Jay Chang
  • Publication number: 20170299019
    Abstract: A transmission for a vehicle may include a first planetary gear set, a second planetary gear set, a third, planetary gear set, and a fourth planetary gear set each including three rotary elements, and a plurality of friction members, in which the friction members are connected to at least one or more of the rotary elements of the planetary gear sets and control rotation of the rotary elements.
    Type: Application
    Filed: June 28, 2017
    Publication date: October 19, 2017
    Applicants: HYUNDAI MOTOR COMPANY, KIA MOTORS CORPORATION
    Inventors: SEONG WOOK JI, KANG SOO SEO, JAY CHANG KOOK, SEONG WOOK HWANG, HYU TAE SHIM, WON MIN CHO, HYUN SIK KWON, WOOK JIN JANG, MYEONG HOON NOH
  • Patent number: 9780003
    Abstract: A method of forming a Bipolar Junction Transistor (BJT) includes forming an elongated collector line, forming an elongated emitter line parallel to the collector line, and forming an elongated base line parallel to the collector line and positioned between the collector line and the base line. The emitter line, the base line, and the collector line are formed over fin structures.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: October 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hsin Hu, Min-chang Liang, Sun-Jay Chang, Shien-Yang Wu
  • Patent number: 9755075
    Abstract: Disclosed are methods to form a FinFET diode of high efficiency, designed to resolve the degradation problem with a conventional FinFET diode arising from reduced active area, and a method of fabrication. The FinFET diode has a doped substrate, two spaced-apart groups of semiconductor fin structures, dielectric layers formed between the two groups and among the fin structures for insulation, a plurality of gate structures perpendicularly traversing both groups of the fin structures, and two groups of semiconductor strips respectively formed lengthwise upon the two groups of the fin structures. The two groups of semiconductor strips are doped to have opposite conductivity types, p-type and n-type. In an embodiment, the FinFET diode further has metal contacts formed upon the semiconductor strips. In another embodiment, the semiconductor strips may be integrally formed with the fin structures by epitaxial growth and in-situ doped.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: September 5, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Hsueh-Shih Fan, Ching-Fang Huang, Chia-Hsin Hu, Min-Chang Liang, Sun-Jay Chang, Shien-Yang Wu, Wen-Hsing Hsieh
  • Publication number: 20170199640
    Abstract: An electronic device has a plurality of user interfaces. The electronic device is configured to display different application programs in different interfaces. The electronic device includes a storage module, a biometric identification module, a determining module and a user interface changing module. The storage module stores biometric identification data and a relationship between the at least one biometric identification data and the different user interfaces. The biometric identification module obtains a biometric identification data on a preset area of the electronic device. The determining module determines whether the obtained biometric identification data is consistent with a stored biometric identification data in the storage module. The interface changing module changes the user interface of the electronic device according to the obtained biometric identification data and the relationship. The present disclosure also provides a user interface changing method.
    Type: Application
    Filed: June 14, 2016
    Publication date: July 13, 2017
    Inventors: HOW-WEN CHIEN, SUNG-JAY CHANG
  • Patent number: 9679992
    Abstract: A fin field effect transistor (FinFET) and a method of forming the same are introduced. In an embodiment, trenches are formed in a substrate, wherein a region between adjacent trenches defines a fin. A dielectric material is formed in the trenches. A part of the substrate is doped and a region of high dopant concentration and a region of low dopant concentration are formed. Gate stacks are formed, portions of the fins are removed and source/drain regions are epitaxially grown in the regions of high/low dopant concentration. Contacts are formed to provide electrical contacts to source/gate/drain regions.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: June 13, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hsin Hu, Sun-Jay Chang