Patents by Inventor Jay Chunsup Yun
Jay Chunsup Yun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11194683Abstract: The disclosure describes techniques for a self-test of a graphics processing unit (GPU) independent of instructions from another processing device. The GPU may perform the self-test in response to a determination that the GPU enters an idle mode. The self-test may be based on information indicating a safety level, where the safety level indicates how many faults in circuits or memory blocks of the GPU need to be detected.Type: GrantFiled: March 11, 2020Date of Patent: December 7, 2021Assignee: QUALCOMM IncorporatedInventors: Rahul Gulati, Andrew Evan Gruber, Brendon Lewis Johnson, Jay Chunsup Yun, Donghyun Kim, Alex Kwang Ho Jong, Anshuman Saxena
-
Publication number: 20200210299Abstract: The disclosure describes techniques for a self-test of a graphics processing unit (GPU) independent of instructions from another processing device. The GPU may perform the self-test in response to a determination that the GPU enters an idle mode. The self-test may be based on information indicating a safety level, where the safety level indicates how many faults in circuits or memory blocks of the GPU need to be detected.Type: ApplicationFiled: March 11, 2020Publication date: July 2, 2020Inventors: Rahul GULATI, Andrew Evan GRUBER, Brendon Lewis JOHNSON, Jay Chunsup YUN, Donghyun KIM, Alex Kwang Ho JONG, Anshuman SAXENA
-
Patent number: 10628274Abstract: The disclosure describes techniques for a self-test of a graphics processing unit (GPU) independent of instructions from another processing device. The GPU may perform the self-test in response to a determination that the GPU enters an idle mode. The self-test may be based on information indicating a safety level, where the safety level indicates how many faults in circuits or memory blocks of the GPU need to be detected.Type: GrantFiled: December 5, 2017Date of Patent: April 21, 2020Assignee: QUALCOMM IncorporatedInventors: Rahul Gulati, Andrew Evan Gruber, Brendon Lewis Johnson, Jay Chunsup Yun, Donghyun Kim, Alex Kwang Ho Jong, Anshuman Saxena
-
Patent number: 10521321Abstract: A graphics processing unit (GPU) of a GPU subsystem of a computing device operates in a first rendering mode to process graphics data to produce a first image. The GPU operates in a second rendering mode to process the graphics data to produce a second image. The computing device detects whether a fault has occurred in the GPU subsystem based at least in part on comparing the first image with the second image.Type: GrantFiled: December 21, 2017Date of Patent: December 31, 2019Assignee: QUALCOMM IncorporatedInventors: Alex Kwang Ho Jong, Jay Chunsup Yun, Donghyun Kim, Rahul Gulati, Brendon Lewis Johnson, Andrew Evan Gruber
-
Patent number: 10467723Abstract: A graphics processing unit (GPU) of a GPU subsystem of a computing device processes graphics data to produce a plurality of portions of a first image, and to produce a plurality of portions of a second image. The GPU generates a plurality of data integrity check values associated with the plurality of portions of the first image, and a plurality of data integrity check values associated with the plurality of portions of the second image. The GPU determines whether each of the plurality of portions of the second image matches a corresponding portion of the first image. The GPU determines, prior to producing every portion of the second image, whether an operational fault has occurred in the GPU subsystem based at least in part the determination of whether each of the plurality of portions of the second image matches a corresponding portion of the first image.Type: GrantFiled: December 21, 2017Date of Patent: November 5, 2019Assignee: QUALCOMM IncorporatedInventors: Brendon Lewis Johnson, Andrew Evan Gruber, Jay Chunsup Yun, Rahul Gulati, Donghyun Kim, Alex Kwang Ho Jong
-
Patent number: 10467774Abstract: Techniques of this disclosure may include processing data using one or more processors to produce a first image, including storing intermediate first results of processing the data in at least one internal memory of the one or more processors according to a first memory access pattern, processing the data using the one or more processors to produce a second image, including storing intermediate second results of processing the data in the at least one internal memory of the one or more processors according to a second memory access pattern, wherein the second memory access pattern is different than the first memory access pattern, comparing the first image to the second image, and generating an interrupt if the comparison indicates that the first image is different than the second image.Type: GrantFiled: November 6, 2017Date of Patent: November 5, 2019Assignee: QUALCOMM IncorporatedInventors: Andrew Evan Gruber, Rahul Gulati, Brendon Lewis Johnson, Jay Chunsup Yun, Alex Kwang Ho Jong, Donghyun Kim
-
Publication number: 20190197651Abstract: A graphics processing unit (GPU) of a GPU subsystem of a computing device processes graphics data to produce a plurality of portions of a first image, and to produce a plurality of portions of a second image. The GPU generates a plurality of data integrity check values associated with the plurality of portions of the first image, and a plurality of data integrity check values associated with the plurality of portions of the second image. The GPU determines whether each of the plurality of portions of the second image matches a corresponding portion of the first image. The GPU determines, prior to producing every portion of the second image, whether an operational fault has occurred in the GPU subsystem based at least in part the determination of whether each of the plurality of portions of the second image matches a corresponding portion of the first image.Type: ApplicationFiled: December 21, 2017Publication date: June 27, 2019Inventors: Brendon Lewis Johnson, Andrew Evan Gruber, Jay Chunsup Yun, Rahul Gulati, Donghyun Kim, Alex Kwang Ho Jong
-
Publication number: 20190196926Abstract: A graphics processing unit (GPU) of a GPU subsystem of a computing device operates in a first rendering mode to process graphics data to produce a first image. The GPU operates in a second rendering mode to process the graphics data to produce a second image. The computing device detects whether a fault has occurred in the GPU subsystem based at least in part on comparing the first image with the second image.Type: ApplicationFiled: December 21, 2017Publication date: June 27, 2019Inventors: Alex Kwang Ho Jong, Jay Chunsup Yun, Donghyun Kim, Rahul Gulati, Brendon Lewis Johnson, Andrew Evan Gruber
-
Publication number: 20190171538Abstract: The disclosure describes techniques for a self-test of a graphics processing unit (GPU) independent of instructions from another processing device. The GPU may perform the self-test in response to a determination that the GPU enters an idle mode. The self-test may be based on information indicating a safety level, where the safety level indicates how many faults in circuits or memory blocks of the GPU need to be detected.Type: ApplicationFiled: December 5, 2017Publication date: June 6, 2019Inventors: Rahul Gulati, Andrew Evan Gruber, Brendon Lewis Johnson, Jay Chunsup Yun, Donghyun Kim, Alex Kwang Ho Jong, Anshuman Saxena
-
Publication number: 20190139263Abstract: Techniques of this disclosure may include processing data using one or more processors to produce a first image, including storing intermediate first results of processing the data in at least one internal memory of the one or more processors according to a first memory access pattern, processing the data using the one or more processors to produce a second image, including storing intermediate second results of processing the data in the at least one internal memory of the one or more processors according to a second memory access pattern, wherein the second memory access pattern is different than the first memory access pattern, comparing the first image to the second image, and generating an interrupt if the comparison indicates that the first image is different than the second image.Type: ApplicationFiled: November 6, 2017Publication date: May 9, 2019Inventors: Andrew Evan Gruber, Rahul Gulati, Brendon Lewis Johnson, Jay Chunsup Yun, Alex Kwang Ho Jong, Donghyun Kim
-
Patent number: 10013735Abstract: A method and manufacture for graphics processing in which a first line of raw Bayer data and a second line of raw Bayer data are received. Each two-by-two array of a plurality of non-overlapping two-by-two arrays of the first line of raw Bayer data and the second line of raw Bayer data is mapped as a separate corresponding texel to provide a plurality of texel. At least one operation is performed on at least one of the plurality of texels.Type: GrantFiled: August 26, 2015Date of Patent: July 3, 2018Assignee: QUALCOMM IncorporatedInventors: Jay Chunsup Yun, Liang Li, Vijay Ganugapati, Xujie Zhang
-
Patent number: 9659341Abstract: A texture pipe of a graphics processing unit (GPU) may receive a texture data. The texture pipe may perform a block-based operation on the texture data, wherein the texture data comprises one or more blocks of texels. Shader processors of the GPU may process graphics data concurrently with the texture pipe performing the block-based operation. The texture pipe may output a result of performing the block-based operation on the one or more texture data.Type: GrantFiled: June 24, 2015Date of Patent: May 23, 2017Assignee: QUALCOMM IncorporatedInventors: Javier Ignacio Girado, Jay Chunsup Yun, Vineet Goel
-
Patent number: 9646359Abstract: An example method of filtering in a graphics processing unit (GPU) may include storing, by a texture engine of the GPU, filter coefficients of a filter as a texture memory object (TMO) in a texture cache of the GPU in response to a first instruction. The method may include retrieving, by the texture engine, filter coefficients from the texture cache in response to a second instruction. The method may include storing, by the texture engine, pixel data in the texture cache of the GPU in response to the second instruction. The pixel data may include one or more pixel values. The method may include filtering, by the texture engine, the pixel data stored in the texture cache using the retrieved filter coefficients.Type: GrantFiled: February 6, 2015Date of Patent: May 9, 2017Assignee: QUALCOMM IncorporatedInventors: Elina Kamenetskaya, Javier Ignacio Girado, Liang Li, Jay Chunsup Yun, Vineet Goel
-
Publication number: 20160217548Abstract: A method and manufacture for graphics processing in which a first line of raw Bayer data and a second line of raw Bayer data are received. Each two-by-two array of a plurality of non-overlapping two-by-two arrays of the first line of raw Bayer data and the second line of raw Bayer data is mapped as a separate corresponding texel to provide a plurality of texel. At least one operation is performed on at least one of the plurality of texels.Type: ApplicationFiled: August 26, 2015Publication date: July 28, 2016Inventors: Jay Chunsup Yun, Liang Li, Vijay Ganugapati, Xujie Zhang
-
Publication number: 20160180548Abstract: This disclosure describes techniques for performing filtering in a graphics processing unit (GPU), The GPU may include a texture engine and a texture memory configured to store pixels and filter coefficients and at least one processor. The at least one processor may be configured to: store filter coefficients as a texture memory object (TMO) in the texture memory accessible to the texture engine in response to a first instruction, retrieve the filter coefficients from the texture memory in response to a second instruction, store pixels from the texture memory in a texture cache of the texture engine in response to the second instruction, and filter the pixels using the retrieved filter coefficients.Type: ApplicationFiled: February 6, 2015Publication date: June 23, 2016Inventors: Elina Kamenetskaya, Javier Ignacio Girado, Liang Li, Jay Chunsup Yun, Vineet Goel
-
Publication number: 20150379676Abstract: A texture pipe of a graphics processing unit (GPU) may receive a texture data. The texture pipe may perform a block-based operation on the texture data, wherein the texture data comprises one or more blocks of texels. Shader processors of the GPU may process graphics data concurrently with the texture pipe performing the block-based operation. The texture pipe may output a result of performing the block-based operation on the one or more texture data.Type: ApplicationFiled: June 24, 2015Publication date: December 31, 2015Inventors: Javier Ignacio Girado, Jay Chunsup Yun, Vineet Goel
-
Publication number: 20150261651Abstract: The techniques described in this disclosure are directed to validating an application that is to be executed on a graphics processing unit (GPU). For example, a validation server device may receive code of the application. The validation server device may provide some level of assurance that the application satisfies one or more performance criteria. In this manner, the probability of a problematic application executing on the device that includes the GPU may be reduced.Type: ApplicationFiled: June 1, 2015Publication date: September 17, 2015Inventors: Alexei V. Bourd, Jay Chunsup Yun
-
Patent number: 9075913Abstract: The techniques described in this disclosure are directed to validating an application that is to be executed on a graphics processing unit (GPU). For example, a validation server device may receive code of the application. The validation server device may provide some level of assurance that the application satisfies one or more performance criteria. In this manner, the probability of a problematic application executing on the device that includes the GPU may be reduced.Type: GrantFiled: February 27, 2012Date of Patent: July 7, 2015Assignee: QUALCOMM IncorporatedInventors: Alexei V. Bourd, Jay Chunsup Yun
-
Publication number: 20130227521Abstract: The techniques described in this disclosure are directed to validating an application that is to be executed on a graphics processing unit (GPU). For example, a validation server device may receive code of the application. The validation server device may provide some level of assurance that the application satisfies one or more performance criteria. In this manner, the probability of a problematic application executing on the device that includes the GPU may be reduced.Type: ApplicationFiled: February 27, 2012Publication date: August 29, 2013Applicant: QUALCOMM INCORPORATEDInventors: Alexei V. Bourd, Jay Chunsup Yun
-
Patent number: 7921274Abstract: A computer addressing mode and memory access method rely on a memory segment identifier and a memory segment mask for indicating memory locations. In this addressing mode, a processor receives an instruction comprising the memory segment identifier and memory segment mask. The processor employs a two-level address decoding scheme to access individual memory locations. Under this decoding scheme, the processor decodes the memory segment identifier to select a particular memory segment. Each memory segment includes a predefined number of memory locations. The processor selects memory locations within the memory segment based on mask bits set in the memory segment mask. The disclosed addressing mode is advantageous because it allows non-consecutive memory locations to be efficiently accessed.Type: GrantFiled: April 19, 2007Date of Patent: April 5, 2011Assignee: QUALCOMM IncorporatedInventors: Bo Zhang, Guofang Jiao, Yun Du, Jay Chunsup Yun