Patents by Inventor Jay Fleischman

Jay Fleischman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210097002
    Abstract: A processing system includes a processor, a memory, and an operating system that are used to allocate a page table caching memory object (PTCM) for a user of the processing system. An allocation of the PTCM is requested from a PTCM allocation system. In order to allocate the PTCM, a plurality of physical memory pages from a memory are allocated to store a PTCM page table that is associated with the PTCM. A lockable region of a cache is designated to hold a copy of the PTCM page table, after which the lockable region of the cache is subsequently locked. The PTCM page table is populated with page table entries associated with the PTCM and copied to the locked region of the cache.
    Type: Application
    Filed: September 27, 2019
    Publication date: April 1, 2021
    Inventors: Derrick Allen AGUREN, Eric H. VAN TASSELL, Gabriel H. LOH, Jay FLEISCHMAN
  • Publication number: 20210089462
    Abstract: Systems, apparatuses, and methods for employing system probe filter aware last level cache insertion bypassing policies are disclosed. A system includes a plurality of processing nodes, a probe filter, and a shared cache. The probe filter monitors a rate of recall probes that are generated, and if the rate is greater than a first threshold, then the system initiates a cache partitioning and monitoring phase for the shared cache. Accordingly, the cache is partitioned into two portions. If the hit rate of a first portion is greater than a second threshold, then a second portion will have a non-bypass insertion policy since the cache is relatively useful in this scenario. However, if the hit rate of the first portion is less than or equal to the second threshold, then the second portion will have a bypass insertion policy since the cache is less useful in this case.
    Type: Application
    Filed: September 24, 2019
    Publication date: March 25, 2021
    Inventors: Paul James Moyer, Jay Fleischman
  • Patent number: 10700954
    Abstract: A system includes a multi-core processor that includes a scheduler. The multi-core processor communicates with a system memory and an operating system. The multi-core processor executes a first process and a second process. The system uses the scheduler to control a use of a memory bandwidth by the second process until a current use in a control cycle by the first process meets a first setpoint of use for the first process when the first setpoint is at or below a latency sensitive (LS) floor or a current use in the control cycle by the first process exceeds the LS floor when the first setpoint exceeds the LS floor.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: June 30, 2020
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Douglas Benson Hunt, Jay Fleischman
  • Publication number: 20200065108
    Abstract: Systems and methods selectively bypass address-generation hardware in processor instruction pipelines. In an embodiment, a processor includes an address-generation stage and an address-generation-bypass-determination unit (ABDU). The ABDU receives a load/store instruction. If an effective address for the load/store instruction is not known at the ABDU, the ABDU routes the load/store instruction via the address-generation stage of the processor. If, however, the effective address of the load/store instruction is known at the ABDU, the ABDU routes the load/store instruction to bypass the address-generation stage of the processor.
    Type: Application
    Filed: August 21, 2018
    Publication date: February 27, 2020
    Inventors: ANDREJ KOCEV, JAY FLEISCHMAN, KAI TROESTER, JOHNNY C. CHU, TIM J. WILKENS, NEIL MARKETKAR, MICHAEL W. LONG
  • Publication number: 20190190805
    Abstract: A system includes a multi-core processor that includes a scheduler. The multi-core processor communicates with a system memory and an operating system. The multi-core processor executes a first process and a second process. The system uses the scheduler to control a use of a memory bandwidth by the second process until a current use in a control cycle by the first process meets a first setpoint of use for the first process when the first setpoint is at or below a latency sensitive (LS) floor or a current use in the control cycle by the first process exceeds the LS floor when the first setpoint exceeds the LS floor.
    Type: Application
    Filed: December 20, 2017
    Publication date: June 20, 2019
    Inventors: Douglas Benson HUNT, Jay FLEISCHMAN
  • Publication number: 20190179643
    Abstract: A coprocessor such as a floating-point unit includes a pipeline that is partitioned into a first portion and a second portion. A controller is configured to provide control signals to the first portion and the second portion of the pipeline. A first physical distance traversed by control signals propagating from the controller to the first portion of the pipeline is shorter than a second physical distance traversed by control signals propagating from the controller to the second portion of the pipeline. A scheduler is configured to cause a physical register file to provide a first subset of bits of an instruction to the first portion at a first time. The physical register file provides a second subset of the bits of the instruction to the second portion at a second time subsequent to the first time.
    Type: Application
    Filed: December 11, 2017
    Publication date: June 13, 2019
    Inventors: Jay FLEISCHMAN, Michael ESTLICK, Michael Christopher SEDMAK, Erik SWANSON, Sneha V. DESAI
  • Publication number: 20190179396
    Abstract: A pipeline includes a first portion configured to process a first subset of bits of an instruction and a second portion configured to process a second subset of the bits of the instruction. A first clock mesh is configured to provide a first clock signal to the first portion of the pipeline. A second clock mesh is configured to provide a second clock signal to the second portion of the pipeline. The first and second clock meshes selectively provide the first and second clock signals based on characteristics of in-flight instructions that have been dispatched to the pipeline but not yet retired. In some cases, a physical register file is configured to store values of bits representative of instructions. Only the first subset is stored in the physical register file in response to the value of the zero high bit indicating that the second subset is equal to zero.
    Type: Application
    Filed: December 11, 2017
    Publication date: June 13, 2019
    Inventors: Jay FLEISCHMAN, Michael ESTLICK, Michael Christopher SEDMAK, Erik SWANSON, Sneha V. DESAI
  • Patent number: 10223162
    Abstract: Systems, apparatuses, and methods for tracking system resource utilization of guest virtual machines (VMs). Counters may be maintained to track resource utilization of different system resources by different guest VMs executing on the system. When a guest VM initiates execution, stored values may be loaded into the resource utilization counters. While the guest VM executes, the counters may track the resource utilization of the guest VM. When the guest VM terminates execution, the counter values may be written to a virtual machine control block (VMCB) corresponding to the guest VM. Scaling factors may be applied to the counter values to normalize the values prior to writing the values to the VMCB. A cloud computing environment may utilize the tracking mechanisms to guarantee resource utilization levels in accordance with users' service level agreements.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: March 5, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael T. Clark, Jay Fleischman, Thaddeus S. Fortenberry, Maurice B. Steinman
  • Patent number: 9910638
    Abstract: Square root operations in a computer processor are disclosed. A first iteration for calculating partial results of a square root operation is performed in a larger number of cycles than remaining iterations. The first iteration requires calculation of a first digit that is larger than the subsequent digits. The first iteration thus requires multiplication of values that are larger than corresponding values for the subsequent other digits. By splitting the first digit into two parts, the required multiplications can be performed in less time than if the first digit were not split. Performing these multiplications in less time reduces the total delay for clock cycles associated with the first digit calculations, which increases the possible clock frequency allowed. A multiply-and-accumulate unit that performs either packed-single operations or double-precision operations may be used, along with a combined division/square root unit for simultaneous execution of division and square root operations.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: March 6, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Hanbing Liu, John Kelley, Michael Estlick, Erik Swanson, Jay Fleischman
  • Publication number: 20180060039
    Abstract: Square root operations in a computer processor are disclosed. A first iteration for calculating partial results of a square root operation is performed in a larger number of cycles than remaining iterations. The first iteration requires calculation of a first digit that is larger than the subsequent digits. The first iteration thus requires multiplication of values that are larger than corresponding values for the subsequent other digits. By splitting the first digit into two parts, the required multiplications can be performed in less time than if the first digit were not split. Performing these multiplications in less time reduces the total delay for clock cycles associated with the first digit calculations, which increases the possible clock frequency allowed. A multiply-and-accumulate unit that performs either packed-single operations or double-precision operations may be used, along with a combined division/square root unit for simultaneous execution of division and square root operations.
    Type: Application
    Filed: August 25, 2016
    Publication date: March 1, 2018
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Hanbing Liu, John Kelley, Michael Estlick, Erik Swanson, Jay Fleischman
  • Patent number: 9575763
    Abstract: A method includes undoing, in reverse program order, changes in a state of a processing device caused by speculative instructions previously dispatched for execution in the processing device and concurrently deallocating resources previously allocated to the speculative instructions in response to interruption of dispatch of instructions due to a flush of the speculative instructions. A processor device comprises a retire queue to store entries for instructions that are awaiting retirement and a finite state machine. The finite state machine is to interrupt dispatch of instructions in response to a flush of speculative instructions previously dispatched for execution in the processing device and to undo, in reverse program order, changes in a state of the processing device caused by the speculative instructions while concurrently deallocating resources previously allocated to the speculative instructions.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: February 21, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jay Fleischman, Michael Estlick
  • Publication number: 20170031719
    Abstract: Systems, apparatuses, and methods for tracking system resource utilization of guest virtual machines (VMs). Counters may be maintained to track resource utilization of different system resources by different guest VMs executing on the system. When a guest VM initiates execution, stored values may be loaded into the resource utilization counters. While the guest VM executes, the counters may track the resource utilization of the guest VM. When the guest VM terminates execution, the counter values may be written to a virtual machine control block (VMCB) corresponding to the guest VM. Scaling factors may be applied to the counter values to normalize the values prior to writing the values to the VMCB. A cloud computing environment may utilize the tracking mechanisms to guarantee resource utilization levels in accordance with users' service level agreements.
    Type: Application
    Filed: April 13, 2016
    Publication date: February 2, 2017
    Inventors: Michael T. Clark, Jay Fleischman, Thaddeus S. Fortenberry, Maurice B. Steinman
  • Patent number: 9028067
    Abstract: A diseased retina has a blind spot where the center of the retina, called the fovea, exists. A compensation system could comprise first measuring a patient's healthy regions of the retina called PRL. A video camera could be mounted on a table, such as for reading applications, but preferably mounted on an eyeglass frame, capture an area of regard (AR). This AR is sent to a computer which directs a projector (such as a MEMS projector) to direct the AR using his healthy area of his retina. Improvements include adding an eyeball location sensor to keep the AR focused on a moving PRL. Another improvement is dithering the AR image in millimeter sized oscillations on the moving PRL. Reading enhancement software such as SpritzĀ® can be integrated into the computer to display the enhanced text onto the PRL.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: May 12, 2015
    Assignee: Sightex LLC
    Inventors: Jay Fleischman, Jerald A Bovino
  • Publication number: 20140372732
    Abstract: A method includes undoing, in reverse program order, changes in a state of a processing device caused by speculative instructions previously dispatched for execution in the processing device and concurrently deallocating resources previously allocated to the speculative instructions in response to interruption of dispatch of instructions due to a flush of the speculative instructions. A processor device comprises a retire queue to store entries for instructions that are awaiting retirement and a finite state machine. The finite state machine is to interrupt dispatch of instructions in response to a flush of speculative instructions previously dispatched for execution in the processing device and to undo, in reverse program order, changes in a state of the processing device caused by the speculative instructions while concurrently deallocating resources previously allocated to the speculative instructions.
    Type: Application
    Filed: June 14, 2013
    Publication date: December 18, 2014
    Inventors: Jay Fleischman, Michael Estlick
  • Patent number: 8819397
    Abstract: Methods and apparatuses are provided for increased efficiency in a processor via control word prediction. The apparatus comprises an operational unit capable of determining whether an instruction will change a first control word to a second control word for processing dependent instructions. Execution units process the dependent instructions using a predicted control word and compare the second control word to the predicted control word. A scheduling unit causes the execution units to reprocess the dependent instructions when the predicted control word does not match the second control word. The method comprises determining that an instruction will change a first control word to a second control word and processing the dependent instructions using a predicted control word. The second control word is compared to the predicted control word and the dependent instructions are reprocessed using the second control word when the predicted control word does not match the second control word.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: August 26, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael D. Estlick, Jay Fleischman, Debjit Das Sarma, Emil Talpes, Krishnan V. Ramani, Chun Liu
  • Patent number: 8769247
    Abstract: Methods and apparatuses are provided for increased efficiency in a processor via early instruction completion. An apparatus is provided for increased efficiency in a processor via early instruction completion. The apparatus comprises an execution unit for processing instructions and determining whether a later issued instruction is ready for completion or an earlier issued instruction is ready for completion and a retire unit for retiring the later issued instruction when the later instruction is ready for completion or to retire the earlier instruction when later instruction is not ready for completion and the earlier issued instruction has a known good completion status. A method is provided for increased efficiency in a processor via early instruction completion. The method comprises completing an earlier issued instruction having a known good completion status ahead of a later issued instruction when the later issued instruction is not ready for completion.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: July 1, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael D Estlick, Kevin Hurd, Jay Fleischman
  • Patent number: 8671288
    Abstract: Methods and apparatuses are provided for controlling power consumption in a processor (or computational unit thereof). The method comprises monitoring power consumption in a processor (or computational unit) and determining that the power consumption of the processor (or computational unit) exceeds a threshold. Thereafter, instruction issuance if modified (such as by slowing or ceasing instruction issuance) within the processor (or computational unit) until the power consumption is below the threshold. The apparatus comprises a power consumption monitor for determining when power consumption within the processor exceeds a threshold. Upon that determination, a scheduler begins modify instruction issuance to one or more execution units until the power consumption is below the threshold. The modification of instruction issuance can be to slow instruction issuance or cease instruction issuance for a time period or until the power consumption is below the threshold.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: March 11, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jay Fleischman, Michael Estlick, Kevin Hurd
  • Publication number: 20120265966
    Abstract: Methods and apparatuses are provided for increased efficiency in a processor via early instruction completion. An apparatus is provided for increased efficiency in a processor via early instruction completion. The apparatus comprises an execution unit for processing instructions and determining whether a later issued instruction is ready for completion or an earlier issued instruction is ready for completion and a retire unit for retiring the later issued instruction when the later instruction is ready for completion or to retire the earlier instruction when later instruction is not ready for completion and the earlier issued instruction has a known good completion status. A method is provided for increased efficiency in a processor via early instruction completion. The method comprises completing an earlier issued instruction having a known good completion status ahead of a later issued instruction when the later issued instruction is not ready for completion.
    Type: Application
    Filed: April 15, 2011
    Publication date: October 18, 2012
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Michael D. ESTLICK, Kevin HURD, Jay FLEISCHMAN
  • Publication number: 20120226891
    Abstract: Methods and apparatuses are provided for increased efficiency in a processor via control word prediction. The apparatus comprises an operational unit capable of determining whether an instruction will change a first control word to a second control word for processing dependent instructions. Execution units process the dependent instructions using a predicted control word and compare the second control word to the predicted control word. A scheduling unit causes the execution units to reprocess the dependent instructions when the predicted control word does not match the second control word. The method comprises determining that an instruction will change a first control word to a second control word and processing the dependent instructions using a predicted control word. The second control word is compared to the predicted control word and the dependent instructions are reprocessed using the second control word when the predicted control word does not match the second control word.
    Type: Application
    Filed: March 1, 2011
    Publication date: September 6, 2012
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Michael D. ESTLICK, Jay FLEISCHMAN, Debjit Das Sarma, Emil TALPES, Krishnan V. RAMANI, Chun LIU
  • Publication number: 20120191956
    Abstract: Methods and apparatuses are provided for achieving increased processor performance and energy saving via reordering operand mapping as opposed to the actual operand data. The apparatus comprises a plurality of physical registers available for use storing operands and includes a unit capable of mapping logical registers to the plurality of physical registers. A multiplexer then reorders the operands by reordering the mapping of logical registers to the plurality of physical registers, which increases processor performance and energy saving by reordering narrow registers instead of wide registers. The method comprises mapping logical registers storing to physical registers storing operands in a processor and then reordering the mapping to achieve the equivalent of reordering the operands without reordering the operands from the physical registers in the processor.
    Type: Application
    Filed: January 26, 2011
    Publication date: July 26, 2012
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventor: Jay FLEISCHMAN