Abstract: Systems and methods for data visualization in the metaverse with portability to multiple metaverse channels are disclosed. In one embodiment, a method for data visualization in the metaverse with portability to multiple metaverse channels may include: (1) ingesting, by a data rendering computer program, data from a plurality of data sources, each data source associated with an entity; (2) categorizing, by the data rendering computer program, the ingested data into a plurality of categories, wherein each category of data comprises data from a subset of two or more of the plurality of the data sources; and (3) streaming, by the data rendering computer program, one of the categories of data to an immersive input/output device associated with a user over one of a plurality of metaverse channels, wherein the category of data is consumed by the immersive input/output device.

Abstract: In some aspects, the techniques described herein relate to a method including: executing a first query, at a predefined time interval, against a target datastore for insight records related to an entity identifier; storing results of the first query as a record set, wherein the record set includes one or more existing insight records, and wherein each existing insight record includes connection information for connecting to a corresponding insight datastore; executing insight retrieval logic for each insight record in the record set, wherein the insight retrieval logic executes a second query against the corresponding insight datastore and retrieves a new insight value from the corresponding insight datastore; persisting the new insight value in a new insight record in the target datastore; and sending the new insight record as a communication to a recipient.

Abstract: Embodiments disclosed herein include a display. In an embodiment, the display comprises a backplane, and circuitry on the backplane. In an embodiment, a pad with a first width is over the backplane and electrically coupled to the circuitry. In an embodiment, the pad comprises a conductive material. In an embodiment, the display further comprises a light emitting diode (LED) coupled to the pad, where the LED has a second width that is smaller than the first width.

Abstract: Gallium nitride (GaN) integrated circuit technology with multi-layer epitaxy and layer transfer is described. In an example, an integrated circuit structure includes a first channel structure including a plurality of alternating first channel layers and second channel layers, the first channel layers including gallium and nitrogen, and the second layers including gallium, aluminum and nitrogen. A second channel structure is bonded to the first channel structure. The second channel structure includes a plurality of alternating third channel layers and fourth channel layers, the third channel layers including gallium and nitrogen, and the fourth layers including gallium, aluminum and nitrogen.

Abstract: Techniques are disclosed for reducing the time required to read and write data to memory. Data reads and/or writes can be delayed when error correction code (ECC) bits, which are used to detect and/or correct data corruption, are written to memory. Writing ECC bits can take longer in some instances than writing data bits because an ECC write may involve a read/modify/write operation, as opposed to just simply writing the bits to memory. Some latencies associated with writing ECC bits can be hidden by interleaving ECC writes with data writes. However, if insufficient data writes are available for interleaving, hiding such latencies become difficult. Thus, various techniques are disclosed, for example, where ECC writes are deferred until a sufficient number of data writes become available for interleaving. By interleaving ECC writes, the disclosed techniques decrease the overall time required to read and write data to memory.

Abstract: A high-endurance, computation-in-memory processor includes a plurality of memory computation modules (MCMs). Each of the MCMs comprise a plurality of memory arrays and a respective module controller to program the plurality of memory arrays to perform mathematical operations on a data set, as well as communicate with other of the MCMs to control a data flow between the MCMs. An inter-module interconnect transports operational data between the MCMs, and communicates with the MCMs to maintain queues storing the operational data during transport between the MCMs. A digital signal processor (DSP) transmits input data to the MCMs and retrieves processed data output by the MCMs.

Abstract: A co-processor is configured for performing vector matrix multiplication (VMM) to solve computational problems such as partial differential equations (PDEs). An analog Discrete Fourier Transform (DFT) can be implemented by invoking VMM of input signals with Fourier basis functions using analog crossbar arrays. Linear and non-linear PDEs can be solved by implementing spectral PDE solution methods as an alternative to massively discretized finite difference methods, while exploiting inherent parallelism realized through the crossbar arrays. A digital controller interfaces with the crossbar arrays to direct write and read operations to the crossbar arrays.

Abstract: Techniques are disclosed for reducing the time required to read and write data to memory. Data reads and/or writes can be delayed when error correction code (ECC) bits, which are used to detect and/or correct data corruption, are written to memory. Writing ECC bits can take longer in some instances than writing data bits because an ECC write may involve a read/modify/write operation, as opposed to just simply writing the bits to memory. Some latencies associated with writing ECC bits can be hidden by interleaving ECC writes with data writes. However, if insufficient data writes are available for interleaving, hiding such latencies become difficult. Thus, various techniques are disclosed, for example, where ECC writes are deferred until a sufficient number of data writes become available for interleaving. By interleaving ECC writes, the disclosed techniques decrease the overall time required to read and write data to memory.

Abstract: A memory management unit responds to an invalidate by class command by identifying a marker for a class of cache entries that the invalidate by class command is meant to invalidate. The memory management unit stores the active marker as a retired marker and then sets the active marker to the next available marker. Thereafter, the memory management sends an acknowledgement signal (e.g., to the operating system) while invalidating the cache entries having the class and the retired marker in the background. By correlating markers with classes of cache entries, the memory management can more quickly respond to class invalidation requests.

Abstract: A memory management unit responds to an invalidate by class command by identifying a marker for a class of cache entries that the invalidate by class command is meant to invalidate. The memory management unit stores the active marker as a retired marker and then sets the active marker to the next available marker. Thereafter, the memory management sends an acknowledgement signal (e.g., to the operating system) while invalidating the cache entries having the class and the retired marker in the background. By correlating markers with classes of cache entries, the memory management can more quickly respond to class invalidation requests.

Abstract: A co-processor is configured for performing vector matrix multiplication (VMM) to solve computational problems such as partial differential equations (PDEs). An analog Discrete Fourier Transform (DFT) can be implemented by invoking VMM of input signals with Fourier basis functions using analog crossbar arrays. Linear and non-linear PDEs can be solved by implementing spectral PDE solution methods as an alternative to massively discretized finite difference methods, while exploiting inherent parallelism realized through the crossbar arrays. A digital controller interfaces with the crossbar arrays to direct write and read operations to the crossbar arrays.

Abstract: A co-processor is configured for performing vector matrix multiplication (VMM) to solve computational problems such as partial differential equations (PDEs). An analog Discrete Fourier Transform (DFT) can be implemented by invoking VMM of input signals with Fourier basis functions using analog crossbar arrays. Linear and non-linear PDEs can be solved by implementing spectral PDE solution methods as an alternative to massively discretized finite difference methods, while exploiting inherent parallelism realized through the crossbar arrays. The analog crossbar array can be implemented in CMOS and memristors or a hybrid solution including a combination of CMOS and memristors.

Abstract: In accordance with embodiments of the present technology, region based selective error detection and correction techniques provide for the tradeoff between the safety of error detection and error correction (EDEC) protection, and the higher bandwidth and capacity of non-EDEC protection for different uses.

Abstract: Embodiments of the claimed subject matter provide systems and methods for protecting data in dynamically allocated regions of memory. The method can include receiving the read request where the read request comprises a virtual address associated with a memory and determining a physical address associated with the virtual address. The further includes determining whether the physical address associated with the virtual address is read protected and determining whether the read request is from a component allowed to access read protected memory. The read protected memory was dynamically allocated on a per page basis. The method further includes in response to determining that the read request is to a read protected physical address and determining that the component is allowed to access read protected memory, sending the data from the physical address in the memory.

Abstract: A co-processor is configured for performing vector matrix multiplication (VMM) to solve computational problems such as partial differential equations (PDEs). An analog Discrete Fourier Transform (DFT) can be implemented by invoking VMM of input signals with Fourier basis functions using analog crossbar arrays. Linear and non-linear PDEs can be solved by implementing spectral PDE solution methods as an alternative to massively discretized finite difference methods, while exploiting inherent parallelism realized through the crossbar arrays. The analog crossbar array can be implemented in CMOS and memristors or a hybrid solution including a combination of CMOS and memristors.

Abstract: An image processor includes an analog correlator for providing correlation information among a pair of stereo images. The image processor includes an analog-to-digital converter (ADC), an analog correlator, and a digital processor. The ADC generates digital data corresponding to analog data of a plurality of images, the digital data being stored to a memory. The analog correlator circuit calculates correlation information among the plurality of images based on the analog data. The digital processor processes the digital data based on the correlation information to provide alignment of the images.

Abstract: Embodiments of the claimed subject matter provide systems and methods for protecting data in dynamically allocated regions of memory. The method can include receiving the read request where the read request comprises a virtual address associated with a memory and determining a physical address associated with the virtual address. The further includes determining whether the physical address associated with the virtual address is read protected and determining whether the read request is from a component allowed to access read protected memory. The read protected memory was dynamically allocated on a per page basis. The method further includes in response to determining that the read request is to a read protected physical address and determining that the component is allowed to access read protected memory, sending the data from the physical address in the memory.

Abstract: Embodiments provide for dramatically improved interference resistance in advanced communications applications, where the frequency range can exceed 1 GHz. Such embodiments may be implemented using wideband technology to provide a wideband compressive sampling architecture that is capable of superior interference rejection through RF front end cancellation.

Abstract: Embodiments provide for dramatically improved interference resistance in advanced communications applications, where the frequency range can exceed 1 GHz. Such embodiments may be implemented using wideband technology to provide a wideband compressive sampling architecture that is capable of superior interference rejection through RF front end cancellation.