Patents by Inventor Jay H. Angle

Jay H. Angle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6877667
    Abstract: Antenna errors are corrected in an integrated circuit design utilizing spare gates distributed throughout the integrated circuit. An integrated circuit in accordance with the invention includes standard cells interspersed with spare gates. For example, the circuit may include one or more rows of spare gates arranged between groups of rows of standard cells, or islands of spare gates arranged between groups of rows of standard cells. A signal line of the integrated circuit having a detected antenna error associated therewith is coupled via one or more conductors associated with at least one metal layer of the integrated circuit to a diode or other antenna error control circuitry formed using at least one of the spare gates. The standard cells and spare gates are preferably placed in accordance with a placement operation of an automated place and route process of a standard cell computer-aided design (CAD) tool.
    Type: Grant
    Filed: August 13, 2003
    Date of Patent: April 12, 2005
    Assignee: Lattice Semiconductor Corporation
    Inventors: Jay H. Angle, Christopher D. Gorsuch, Oscar G. Mercado, Anthony K. Myers, John A. Schadt, Brian W. Yeager
  • Patent number: 6814296
    Abstract: Antenna errors are corrected in an integrated circuit design utilizing spare gates distributed throughout the integrated circuit. An integrated circuit in accordance with the invention includes standard cells interspersed with spare gates. For example, the circuit may include one or more rows of spare gates arranged between groups of rows of standard cells, or islands of spare gates arranged between groups of rows of standard cells. A signal line of the integrated circuit having a detected antenna error associated therewith is coupled via one or more conductors associated with at least one metal layer of the integrated circuit to a diode or other antenna error control circuitry formed using at least one of the spare gates. The standard cells and spare gates are preferably placed in accordance with a placement operation of an automated place and route process of a standard cell computer-aided design (CAD) tool.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: November 9, 2004
    Assignee: Lattice Semiconductor Corp.
    Inventors: Jay H. Angle, Christopher D. Gorsuch, Oscar G. Mercado, Anthony K. Myers, John A. Schadt, Brian W. Yeager
  • Publication number: 20020167042
    Abstract: Antenna errors are corrected in an integrated circuit design utilizing spare gates distributed throughout the integrated circuit. An integrated circuit in accordance with the invention includes standard cells interspersed with spare gates. For example, the circuit may include one or more rows of spare gates arranged between groups of rows of standard cells, or islands of spare gates arranged between groups of rows of standard cells. A signal line of the integrated circuit having a detected antenna error associated therewith is coupled via one or more conductors associated with at least one metal layer of the integrated circuit to a diode or other antenna error control circuitry formed using at least one of the spare gates. The standard cells and spare gates are preferably placed in accordance with a placement operation of an automated place and route process of a standard cell computer-aided design (CAD) tool.
    Type: Application
    Filed: April 30, 2002
    Publication date: November 14, 2002
    Inventors: Jay H. Angle, Christopher D. Gorsuch, Oscar G. Mercado, Anthony K. Myers, John A. Schadt, Brian W. Yeager