Abstract: A memory sense amplifier for a static random access memory includes a pair of transistor amplifiers respective to the bit lines threading the memory. The power consumed is minimized without sacrificing speed of operation by temporarily connecting the source electrodes of the transistor amplifiers to the bit lines to allow them to track the states of the bit lines before a current path is completed to the drains of the transistors to allow them to draw current from the bit lines, thereby minimizing the time that the sense amplifiers are permitted to draw current from the bit lines. In addition, an economy of circuitry is achieved by eliminating the need for a separate latch circuit by disconnecting the sense amplifiers from the bit lines and thereafter enabling them to latch the information state read from the bit lines.

Abstract: A packet switching network that accommodates the appearance of multiple occurrences of packets addressed to the same destination are accommodated. The network includes a recirculating delay block within the switch, and an expander that includes a modest number of multiple appearances of the same address, followed by memories that accept the packets delivered at those multiple appearances, store the packets, and output the stored packets to the user, one at a time, in accordance with a set priority scheme.

Abstract: An orthogonal transform processor comprising a rotator circuit, a look-up table and a communicator circuit. The rotator circuit performs the complex multiplications required of a rotator, the necessary coefficients are supplied by the look-up table, and the communicator circuit is charged with the task of accepting input signals, supplying the rotator with the signals necessary for each iteration, and delivering the resultant output signals. The rotator is realized with a matrix of spatially adjacent interconnected multiplier and adder modules, where each module comprises a portion of each of the multipliers necessary in the rotator.

Abstract: There is disclosed a modular memory cell structure including a data latch, an occupancy bit latch and control logic. Each memory cell has access to the occupancy bit status of adjacent cells and to the input, output, control, and status busses. The occupancy status provides positional address information enabling each cell to determine if data in its data latch is the first, intermediate, or last element of a data queue. When a group of memory cells and an initialization circuit are interconnected, a modular integrated circuit design results which can function as either a first in-first out (FIFO) or a last in-first out (LIFO) memory.