Abstract: A system including a first core to execute instructions associated with an application at a first speed based on a first instruction set and a second core to execute the instructions associated with the application at a second speed based on a second instruction set. The first speed is greater than the first speed. The second instruction set is a subset of the first instruction set. A first memory stores an operating system. The operating system includes a kernel that provides services to the application. A core switching module loads into a second memory after the operating system is booted, where the second memory is separate from the first memory, switches execution of the instructions associated with the application between the first core and the second core, and switches the execution of the instructions associated with the application between the first core and the second core transparently to the operating system.

Abstract: A core switching system includes a mode switching module that receives a switch signal to switch operation between a first mode and a second mode. During the first mode, instructions associated with applications are executed by a first asymmetric core, and a second asymmetric core is inactive. During the second mode, the instructions are executed by the second asymmetric core, and the first asymmetric core is inactive. A core activation module stops processing of the applications by the first asymmetric core after interrupts are disabled. A state transfer module transfers a state of the first asymmetric core to the second asymmetric core. The core activation module allows the second asymmetric core to resume execution of the instructions and the interrupts are enabled.

Abstract: A core switching system includes a mode switching module that receives a switch signal to switch operation between a first mode and a second mode. During the first mode, instructions associated with applications are executed by a first asymmetric core, and a second asymmetric core is inactive. During the second mode, the instructions are executed by the second asymmetric core, and the first asymmetric core is inactive. A core activation module stops processing of the applications by the first asymmetric core after interrupts are disabled. A state transfer module transfers a state of the first asymmetric core to the second asymmetric core. The core activation module allows the second asymmetric core to resume execution of the instructions and the interrupts are enabled.

Abstract: A system includes a first asymmetric core, a second asymmetric core, and a core switching module. The first asymmetric core executes an application when the system operates in a first mode and is inactive when the system operates in a second mode. The second asymmetric core executes the application when the system operates in the second mode. The core switching module switches operation of the system between the first mode and the second mode. The core switching module selectively stops processing of the application by the first asymmetric core after receiving a first control signal. The core switching module transfers a first state of the first asymmetric core to the second asymmetric core. The second asymmetric core resumes executing the application in the second mode.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit has a voltage regulator and a clock divider that may be used to adjust the operational frequency and/or voltage potential of the integrated circuit to reduce the power consumption of the integrated circuit while in operation.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit has a voltage regulator and a clock divider that may be used to adjust the operational frequency and/or voltage potential of the integrated circuit to reduce the power consumption of the integrated circuit while in operation.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit has a voltage regulator and a clock divider that may be used to adjust the operational frequency and/or voltage potential of the integrated circuit to reduce the power consumption of the integrated circuit while in operation.

Abstract: Briefly, in accordance with one embodiment of the invention, a system includes: a processor, a voltage regulator, and a memory. The voltage regulator is coupled to the processor to adjust the operating voltage of the processor. The memory is coupled to the processor by a memory bus. The memory has stored on it processor instructions that, when executed by the processor, result in modification of the operating frequency of the processor and result in adjustment of the operating voltage of the processor, based, at least in part, on dynamic changes in the processing load of the processor.

Abstract: Briefly, in accordance with one embodiment of the invention, a system includes: a processor, a voltage regulator, and a memory. The voltage regulator is coupled to the processor to adjust the operating voltage of the processor. The memory is coupled to the processor by a memory bus. The memory has stored on it processor instructions that, when executed by the processor, result in modification of the operating frequency of the processor and result in adjustment of the operating voltage of the processor, based, at least in part, on dynamic changes in the processing load of the processor.

Abstract: Briefly, in accordance with one embodiment of the invention, a system includes: a processor, a voltage regulator, and a memory. The voltage regulator is coupled to the processor to adjust the operating voltage of the processor. The memory is coupled to the processor by a memory bus. The memory has stored on it processor instructions that, when executed by the processor, result in modification of the operating frequency of the processor and result in adjustment of the operating voltage of the processor, based, at least in part, on dynamic changes in the processing load of the processor.

Abstract: A processor for executing a set of instructions, where each instruction in said set of instructions includes a set of operand references. The processor includes an instruction decoder for extracting the set of operand references from each instruction in the set of instructions; a register file decoder connected to the instruction decoder for receiving the set of operand references and generating a set of register data select signals; and, a register file connected to the register file decoder for receiving the set of register data select signals. Further, the register file includes: a set of registers; a first set of scoreboard bits; and, a second set of scoreboard bits; wherein for each signal in the set of register data select signals, the register file outputs: (1) a corresponding register from the set of registers; (2) a first corresponding scoreboard bit from the first set of scoreboard bits; and, (3) a second corresponding scoreboard bit from the second set of scoreboard bits.

Abstract: A processor core suitable for use with a wide variety of instruction fetch units. The processor core contains a plurality of pipe stages including an instruction pointer generation stage and a decode stage. The core bundles all control necessary for downstream pipeline operation with an instruction address in a first stage. The bundle is transmitted outside the core to the instruction fetch unit. The instruction fetch unit fetches the instruction and adds it to the bundle, before forwarding the bundle as modified back within the core and down the pipeline. In this way, an external pipe stage is introduced providing a connection between discontinuous pipe stages in the core. Additionally, by bundling the control signals and address information in a single bundle that traverses the external pipe stage as a group, synchronization concerns are reduced or eliminated.

Abstract: A method and apparatus for hit-dependent flushing of cacheable memory access operations in a bus controller queue is described. The present invention is implemented in the context of a computer system including a microprocessor coupled to an external memory device through an external bus. The processor includes a processor core for issuing memory access operations, a cache, and a bus controller. The bus controller includes a queue having slots for storing pending memory access operations to be sent out over the external bus. After a first memory access operation is issued, the bus controller stores the first memory access operation in a first queue slot before it is determined whether the first operation hits or misses the cache. The bus controller flushes the first operation from the queue if the first operation hits the cache.

Abstract: A microprocessor and method which allows data consistency to be maintained between a memory which is external to the microprocessor and a data cache unit. The microprocessor has a central processing unit coupled to a local bus. A direct memory access unit coupled to the central processing unit for loading data from and storing data to the direct access memory unit. The local bus is coupled to a system bus and has a bus control unit controlling the loading and storing of data on the system bus. The system bus transfers data external to the microprocessor using the bus control unit upon instructions from the central processing unit. A data cache unit is coupled to the local bus and selectively stores a copy of data loaded by the bus control unit and receives a memory address from the local bus during a memory access by either the central processing unit or the direct memory access unit.

Abstract: A dynamically expandable pipeline in a microprocessor. The present invention is used in a microprocessor or a microprocessor in a computer system. The present invention delays execution of a cacheable LOAD instruction by a bus controller for one cycle to allow sufficient time for "hit or miss" detection by a data cache unit. The present invention dynamically expands the instruction pipeline for cacheable LOAD instructions that "miss" an on-chip data cache when the LOAD is followed by another instruction that uses the bus controller. The dynamic pipeline allows time for the "hit or miss" detection by the data cache unit without unnecessarily degrading pipeline performance. The present invention offers increased overall microprocessor and computer system performance by allowing efficient implementation of an on-chip data cache. The present invention provides increased performance without undue or overly complex modifications to existing pipeline or data cache circuits.

Abstract: A method and apparatus for performing bi-endian byte and short accesses in a single endian microprocessor. The present invention is used in a microprocessor or in a microprocessor in a computer system. The present invention provides a single endian microprocessor that promotes sub-word accesses to word accesses with a means for manipulating the two least significant bits of the access address to point to the correct sub-word data returned during an access to bi-endian external memory. The method for manipulating the address bits is also used to allow a single endian data cache to operate with the bi-endian external memory. The two LSBs of the address are manipulated such that the pointer values are A1# and A0# for word promoted byte accesses or cacheable accesses. For word promoted short accesses or cacheable accesses, the pointer values are A1# and A0. The present invention offers increased flexibility in interfacing a single-endian microprocessor with bi-endian systems.