Patents by Inventor Jay J. Nejedlo
Jay J. Nejedlo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10198333Abstract: An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test.Type: GrantFiled: December 23, 2010Date of Patent: February 5, 2019Assignee: INTEL CORPORATIONInventors: Mark B. Trobough, Keshavan K. Tiruvallur, Chinna B. Prudvi, Christian E. Iovin, David W. Grawrock, Jay J. Nejedlo, Ashok N. Kabadi, Travis K. Goff, Evan J. Halprin, Kapila B. Udawatta, Jiun Long Foo, Wee Hoo Cheah, Vui Yong Liew, Selvakumar Raja Gopal, Yuen Tat Lee, Samie B. Samaan, Kip C. Killpack, Neil Dobler, Nagib Z. Hakim, Brian Meyer, William H. Penner, John L. Baudrexl, Russell J. Wunderlich, James J. Grealish, Kyle Markley, Timothy S. Storey, Loren J. McConnell, Lyle E. Cool, Mukesh Kataria, Rahima K. Mohammed, Tieyu Zheng, Yi Amy Xia, Ridvan A. Sahan, Arun R. Ramadorai, Priyadarsan Patra, Edwin E. Parks, Abhijit Davare, Padmakumar Gopal, Bruce Querbach, Hermann W. Gartler, Keith Drescher, Sanjay S. Salem, David C. Florey
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Publication number: 20150127983Abstract: An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and de-bug of a part/platform under test.Type: ApplicationFiled: December 23, 2010Publication date: May 7, 2015Applicant: INTEL CORPORATIONInventors: Mark B. Trobough, Keshavan K. Tiruvallur, Chinna B. Prudvi, Christian E. Iovin, David W. Grawrock, Jay J. Nejedlo, Ashok N. Kabadi, Travis K. Goff, Evan J. Halprin, Kapila B. Udawatta, Jiun Long Foo, Wee Hoo Cheah, Vui Yong Liew, Selvakumar Raja Gopal, Yuen Tat Lee, Samie B. Samaan, Kip C. Killpack, Neil Dobler, Nagib Z. Hakim, Briar Meyer, William H. Penner, John L. Baudrexl, Russell J. Wunderlich, James J. Grealish, Kyle Markley, Timothy S. Storey, Loren J. McConnell, Lyle E. Cool, Mukesh Kataria, Rahima K. Mohammed, Tieyu Zheng, Yi Amy Xia, Ridvan A. Sahan, Arun R. Ramadorai, Priyadarsan Patra, Edwin E. Parks, Abhijit Davare, Padmakumar Gopal, Bruce Querbach, Hermann W. Gartler, Keith Drescher, Sanjay S. Salem, David C. Florey
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Patent number: 8868992Abstract: REUT (Robust Electrical Unified Testing) for memory links is introduced which speeds testing, tool development, and debug. In addition it provides training hooks that have enough performance to be used by BIOS to train parameters and conditions that have not been possible with past implementations. Address pattern generation circuitry is also disclosed.Type: GrantFiled: December 31, 2009Date of Patent: October 21, 2014Assignee: Intel CorporationInventors: Bryan L. Spry, Theodore Z. Schoenborn, Philip Abraham, Christopher P. Mozak, David G. Ellis, Jay J. Nejedlo, Bruce Querbach, Zvika Greenfield, Rony Ghattas, Jayasekhar Tholiyil, Charles D. Lucas, Christopher E. Yunker
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Publication number: 20110161752Abstract: REUT (Robust Electrical Unified Testing) for memory links is introduced which speeds testing, tool development, and debug. In addition it provides training hooks that have enough performance to be used by BIOS to train parameters and conditions that have not been possible with past implementations. Address pattern generation circuitry is also disclosed.Type: ApplicationFiled: December 31, 2009Publication date: June 30, 2011Inventors: BRYAN L. SPRY, THEODORE Z. SCHOENBORN, PHILIP ABRAHAM, CHRISTOPHER P. MOZAK, DAVID G. ELLIS, JAY J. NEJEDLO, BRUCE QUERBACH, ZVIKA GREENFIELD, RONY GHATTAS, JAYASEKHAR THOLIYIL, CHARLES D. LUCAS, CHRISTOPHER E. YUNKER
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Patent number: 7536267Abstract: In some embodiments, built-in self-test logic is provided for an integrated circuit (IC) device having memory controller logic to generate address and command information for accessing a memory device. Driver circuits are on-chip with the memory controller logic. The driver circuits have outputs that are coupled to on-chip signal pads, respectively. The BIST logic is coupled between the driver circuits and the controller logic. The BIST logic is to transmit, at speed, address and command information that has been generated by the controller logic using the driver circuits in a normal mode of operation for the device. In addition, the BIST logic is able to transmit, at speed, test symbols using the driver circuits in a test mode of operation for the IC device, during which a chip-to-chip connection between the IC device and another device is tested. Other embodiments are also described and claimed.Type: GrantFiled: November 28, 2005Date of Patent: May 19, 2009Assignee: Intel CorporationInventors: David Zimmerman, Jay J. Nejedlo
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Patent number: 7464307Abstract: According to one embodiment, a built-in self test (IBIST) architecture/methodology is disclosed. The IBIST provides for testing the functionality of an interconnect (such as a bus) between a transmitter and a receiver component. The IBIST architecture includes a pattern generator and a pattern checker. The pattern checker operates to compare a received plurality of bits (for the pattern generator) with a previously stored plurality of bits.Type: GrantFiled: March 25, 2003Date of Patent: December 9, 2008Assignee: Intel CorporationInventors: Jay J. Nejedlo, Mike Wiznerowicz, David G. Ellis, Richard J. Glass, Andrew W. Martwick, Theodore Z. Schoenborn
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Patent number: 6826100Abstract: A built-in self test (BIST) unit, of a primary integrated circuit (IC) component of a computer system, is programmed or hardwired with a test pattern. The test pattern is launched in multiple test cycles, to test an interconnect bus of the computer system or perform a device validation test of the component. A pin assignment of the pattern is automatically changed after each test cycle, without requiring re-programming of the BIST unit to do so.Type: GrantFiled: March 31, 2003Date of Patent: November 30, 2004Assignee: Intel CorporationInventors: David G. Ellis, Bruce Querbach, Jay J. Nejedlo, Amjad Khan, Sean R. Babcock, Eric S. Gayles, Eshwar Gollapudi
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Publication number: 20040204912Abstract: According to one embodiment, a built-in self test (IBIST) architecture/methodology is disclosed. The IBIST provides for testing the functionality of an interconnect (such as a bus) between a transmitter and a receiver component. The IBIST architecture includes a pattern generator and a pattern checker. The pattern checker operates to compare a received plurality of bits (for the pattern generator) with a previously stored plurality of bits.Type: ApplicationFiled: March 25, 2003Publication date: October 14, 2004Inventors: Jay J. Nejedlo, Mike Wiznerowicz, David G. Ellis, Richard J. Glass, Andrew W. Martwick, Theodore Z. Schoenborn
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Publication number: 20040193986Abstract: An apparatus and method for generating test patterns with an on-die self test circuit (e.g., IBIST) are disclosed. In various embodiments, the IBIST comprises a sub-pattern generator that may include one or more of a storage element for a user-defined sub-pattern, a clock sub-pattern generator, and a constant sub-pattern generator. A multiplexer is used to assemble a test pattern based on a combination of sub-patterns from the sub-pattern generator.Type: ApplicationFiled: March 31, 2003Publication date: September 30, 2004Inventors: Karthisha S. Canagasaby, Victor W. Lee, Jay J. Nejedlo
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Publication number: 20040193976Abstract: A method and apparatus for Interconnect Built-In Self-Test (IBIST) Based System Management Failure Monitoring provides for measuring operating conditions of interconnects between a first device and a second device for system management of a post-production system. Results from the measuring are generated. System management failure monitoring of the post-production system is based on the generated results.Type: ApplicationFiled: March 31, 2003Publication date: September 30, 2004Inventors: Thomas M. Slaight, Jay J. Nejedlo, Russell L. Carr
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Publication number: 20040117708Abstract: An integrated circuit (IC) component of a computer system, intended for use as part of a production version of the system, is provided with a built-in test unit and core function circuitry that are coupled to transfer information over the same I/O buffer circuitry of the component. The test unit is to transfer test information during a test session and to recognize announcement of the test session via an assertion and a deassertion, for predetermined time intervals, of an inter-component signal.Type: ApplicationFiled: March 31, 2003Publication date: June 17, 2004Inventors: David G. Ellis, Bruce Querbach, Jay J. Nejedlo, Amjad Khan, Sean R. Babcock, Eric S. Gayles, Eshwar Gollapudi
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Publication number: 20040117707Abstract: A built-in self test (BIST) unit, of a primary integrated circuit (IC) component of a computer system, is programmed or hardwired with a test pattern. The test pattern is launched in multiple test cycles, to test an interconnect bus of the computer system or perform a device validation test of the component. A pin assignment of the pattern is automatically changed after each test cycle, without requiring re-programming of the BIST unit to do so.Type: ApplicationFiled: March 31, 2003Publication date: June 17, 2004Inventors: David G. Ellis, Bruce Querbach, Jay J. Nejedlo, Amjad Khan, Sean R. Babcock, Eric S. Gayles, Eshwar Gollapudi