Abstract: A graphics controller enhances concurrency among multiple pipelines, provides high throughput to graphics resources between 2D and 3D pipelines spawned by an application, and provides low latency for 2D pipelines spawned by an operating system. The graphics controller includes a command parser, arbitration logic, a BLTBIT engine having first and second operating registers. Graphics commands from the application are routed through the command processor, while graphics commands from the operating system are written to the second operating register. Access signaling bits associated with each operating register for communicating between the arbitration logic and the application and operating system. Graphics commands from application-spawned pipelines are coupled through the command parser to specified graphics resources, including the first operating register. An arbitration scheme assigns higher priority to BLTBIT engine accesses initiated by pipelines spawned by the operating system.