Patents by Inventor Jay Jardosh

Jay Jardosh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250307977
    Abstract: An apparatus to facilitate a pixel reorder buffer in a graphics environment is disclosed. The apparatus includes shared hardware circuitry for processing cores comprising pixel reorder buffer (PRB) circuitry that is to: query a dependency status of threads corresponding to the messages received from the at least one execution resource to determine whether the messages correspond to one of non-dependent threads or dependent threads; populate a non-dependent first-in-first-out (FIFO) of the PRB circuitry with thread identifiers (IDs) of the non-dependent threads corresponding to the messages; populate a dependent FIFO of the PRB circuitry with thread IDs of the dependent threads corresponding to the messages; and arbitrate reads between the non-dependent FIFO and the dependent FIFO based on an oldest thread ID in the non-dependent FIFO and the dependent FIFO, wherein the thread IDs corresponding to a dependency cleared indication are available for read arbitration from the dependent FIFO.
    Type: Application
    Filed: March 29, 2024
    Publication date: October 2, 2025
    Applicant: Intel Corporation
    Inventors: Eric Hoekstra, Jay Jardosh, Pazhani Pillai
  • Patent number: 12293430
    Abstract: Methods, systems and apparatuses provide for graphics processor technology that routes untyped unordered access view (UAV) messages to a next level memory cache, routes typed UAV messages and render target messages to a pixel pipeline, and processes, via the pixel pipeline, the typed UAV messages. The technology can also provide for the pixel pipeline to perform a format conversion of one or more pixels associated with a typed UAV message based on a surface format of a UAV resource, calculate a memory address for each pixel associated with the typed UAV message, and collect a plurality of fragments from processed typed UAV messages.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: May 6, 2025
    Assignee: Intel Corporation
    Inventors: Jay Jardosh, Prasoonkumar Surti, Abhishek R. Appu
  • Publication number: 20220414813
    Abstract: Methods, systems and apparatuses provide for graphics processor technology that routes untyped unordered access view (UAV) messages to a next level memory cache, routes typed UAV messages and render target messages to a pixel pipeline, and processes, via the pixel pipeline, the typed UAV messages. The technology can also provide for the pixel pipeline to perform a format conversion of one or more pixels associated with a typed UAV message based on a surface format of a UAV resource, calculate a memory address for each pixel associated with the typed UAV message, and collect a plurality of fragments from processed typed UAV messages.
    Type: Application
    Filed: June 23, 2021
    Publication date: December 29, 2022
    Inventors: Jay Jardosh, Prasoonkumar Surti, Abhishek R. Appu