Abstract: A data frame switching apparatus has number data ports and a port traffic management unit for each port. Each port traffic management unit includes a physical layer unit for receiving and transmitting data frames, a serial shift register for temporarily storing a portion of each received data frame in serial data format, and a port controller for extracting each data frame's source and destination address from the portion of the data frame stored in the serial shift register. A crossbar switch connects any specified one of the data ports that is receiving a data frame to another one of the data ports so as to transmit the received data frame to a corresponding destination.

Abstract: A data and clock recovery circuit includes a front end circuit for receiving a data signal encoded with a Manchester or other bi-phase level code having a sequence of bit frames, and for outputting a recovered data signal and a recovered clock signal in accordance with transitions in the data signal that overlap with a window signal. A window generation circuit generates the window signal in accordance with a delay control signal, and includes circuitry that delays and transforms the recovered clock signal into the window signal. A delay control circuit generates and adjusts the delay control signal. A phase comparison circuit compares the recovered clock signal with leading and lagging portions of the window signal, and generates signals that adjust the delay control signal when the recovered clock signal overlaps with either of the leading and lagging portions of the signal.

Abstract: A clock and data recovery circuit has an input port for receiving a data signal representing a sequence of data values, a pulse generator, a clock generator and a data storage element. The pulse generator generates a pulse whenever a data value change is detected in the received data signal. The clock generator generates a clock signal having an associated frequency and phase. The clock generator receives each pulse produced by the pulse generator so as to synchronize the clock signal's phase with data value changes on the input port. The data storage element stores data values in the data signal at times dictated by the generated clock signal. The data values stored by the data storage element is the recovered data signal and the generated clock signal is the recovered clock signal.