Abstract: Bandwidth shaping mechanisms in a memory hierarchy operate a first bandwidth shaper on a first memory, such as a cache memory, to shape bandwidth to a second memory, such as a Dynamic Random Access Memory, and replenish the first bandwidth shaper from a second bandwidth shaper based on a hit bandwidth on the first memory.

Abstract: Bandwidth shaping mechanisms in a memory hierarchy operate a first bandwidth shaper on a first memory, such as a cache memory, to shape bandwidth to a second memory, such as a Dynamic Random Access Memory, and replenish the first bandwidth shaper from a second bandwidth shaper based on a hit bandwidth on the first memory.

Abstract: Systems and methods in accordance with the present disclosure can prevent interference of memory operations being performed, for example, by high priority or high safety applications. In various examples, a memory management unit (MMU) can receive, from a client, a request to perform a process. The MMU can select, based at least on an identifier of at least one of the client or the process, a target memory manager of a plurality of memory managers of the MMU. The MMU can cause the target memory manager to perform a memory translation operation for the request.

Abstract: A system and method are provided for implementing multi-stage translation of virtual addresses. The method includes the steps of receiving, at a first memory management unit, a memory request including a virtual address in a first address space, translating the virtual address to generate a second virtual address in a second address space, and transmitting a modified memory request including the second virtual address to a second memory management unit. The second memory management unit is configured to translate the second virtual address to generate a physical address in a third address space. The physical address is associated with a location in a memory.

Abstract: A system and method are provided for protecting data. In operation, a request to read data from memory is received. Additionally, it is determined whether the data is stored in a predetermined portion of the memory. If it is determined that the data is stored in the predetermined portion of the memory, the data and a protect signal are returned for use in protecting the data. In certain embodiments of the invention, data stored in the predetermined portion of the memory may be further processed and written hack to the predetermined portion of the memory. In other embodiments of the invention, such processing may involve unprotected data stored outside the predetermined portion of the memory.

Abstract: A system and method for power management by providing advance notice of events. The method includes snooping a register of an operating system timer to determine a timer period associated with a scheduled event. A unit of a computer system is identified that is in a low power state. A wake up latency of the unit is determined that is based on the low power state. An advance period is determined based on the wake up latency. An advance notice of the operating system timer is triggered based on the timer period and the advance period to wake up the unit.

Abstract: A system and method are provided for implementing multi-stage translation of virtual addresses. The method includes the steps of receiving, at a first memory management unit, a memory request including a virtual address in a first address space, translating the virtual address to generate a second virtual address in a second address space, and transmitting a modified memory request including the second virtual address to a second memory management unit. The second memory management unit is configured to translate the second virtual address to generate a physical address in a third address space. The physical address is associated with a location in a memory.

Abstract: A system and method are provided for protecting data. In operation, a request to read data from memory is received. Additionally, it is determined whether the data is stored in a predetermined portion of the memory. If it is determined that the data is stored in the predetermined portion of the memory, the data and a protect signal are returned for use in protecting the data. In certain embodiments of the invention, data stored in the predetermined portion of the memory may be further processed and written hack to the predetermined portion of the memory. In other embodiments of the invention, such processing may involve unprotected data stored outside the predetermined portion of the memory.

Abstract: A communication system is described providing for access to registers over a control register access bus. The system includes one or more core units including one or more addressable core registers, wherein the units are coupled to the communication bus. The system also includes one or more core clusters (CCLUSTERs) coupled to the one or more core units through the communication bus. The CCLUSTERs provide one or more gateways for transactions to and from the one or more core units. The system also includes a request ordering and coherency (ROC) unit coupled to the CCLUSTERs through the communication bus that is configured for scheduling transactions relating to the registers onto the communication bus. The system also includes the one or more addressable registers that are located in the ROC unit, the CCLUSTERs, and the one or more core units.

Abstract: A system and method for power management by providing advance notice of events. The method includes snooping a register of an operating system timer to determine a timer period associated with a scheduled event. A unit of a computer system is identified that is in a low power state. A wake up latency of the unit is determined that is based on the low power state. An advance period is determined based on the wake up latency. An advance notice of the operating system timer is triggered based on the timer period and the advance period to wake up the unit.

Abstract: A FIFO memory system for multiple input channels, has a channel control logic coupled to a channel input signal. A pointer and flag logic block is coupled to an output of the channel control logic. A memory has an address bus coupled to the channel control logic and the pointer and flag logic.