Patents by Inventor Jay Kumar
Jay Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10290350Abstract: A first write operation is received. The first write operation includes a SET operation. The SET operation is configured to place a cell of the non-volatile memory (NVM) device in a relatively low-resistance state. A second write operation is received. A first electrical pulse is applied to a first cell of the NVM device. The first electrical pulse is applied to place the first cell in the relatively low-resistance state. A second electrical pulse is applied to a second cell of the NVM device. The second electrical pulse is applied before the first electrical pulse has concluded. The second cell and the first cell are both within a single tile of the NVM device.Type: GrantFiled: February 20, 2018Date of Patent: May 14, 2019Assignee: Western Digital Technologies, Inc.Inventors: Zvonimir Z. Bandic, Won Ho Choi, Jay Kumar
-
Patent number: 10283199Abstract: A storage device includes a cross-point non-volatile memory (NVM) device that includes a first subset of cells. Cells of the first subset of cells may share either a bitline or a wordline. There may be at least one buffer cell on a respective bitline or wordline between each adjacent pair of cells from the first subset of cells. The storage device includes a control module. The control module is configured to receive a set of I/O operations. The control module is configured to execute a first subset of the set of I/O operations in parallel across the first subset of cells of the cross-point memory component. The control module may execute the first subset of the set of I/O operations such that I/O operations are not executed at the respective buffer cells.Type: GrantFiled: February 23, 2018Date of Patent: May 7, 2019Assignee: Western Digital Technologies, Inc.Inventors: Zvonimir Z. Bandic, Won Ho Choi, Jay Kumar
-
Publication number: 20180218773Abstract: A storage device includes a cross-point non-volatile memory (NVM) device that includes a first subset of cells. Cells of the first subset of cells may share either a bitline or a wordline. There may be at least one buffer cell on a respective bitline or wordline between each adjacent pair of cells from the first subset of cells. The storage device includes a control module. The control module is configured to receive a set of I/O operations. The control module is configured to execute a first subset of the set of I/O operations in parallel across the first subset of cells of the cross-point memory component. The control module may execute the first subset of the set of I/O operations such that I/O operations are not executed at the respective buffer cells.Type: ApplicationFiled: February 23, 2018Publication date: August 2, 2018Inventors: Zvonimir Z. Bandic, Won Ho Choi, Jay Kumar
-
Publication number: 20180211703Abstract: The present disclosure, in various embodiments, describes three-dimensional (3D) vertical resistive random access memory (ReRAM) structures. In one embodiment, a memory device includes a resistive memory element and a selector coupled in series with the resistive memory element. A turn-on voltage of the selector is greater than a bias voltage of the memory device in an unselected state such that the selector remains in a turn-off state when the memory device is unselected, and the selector is configured to have substantially the same resistance in both a forward bias direction and a reverse bias direction in a turn-on state.Type: ApplicationFiled: May 5, 2017Publication date: July 26, 2018Inventors: Won Ho Choi, Jay Kumar, Daniel Bedau, Zvonimir Z. Bandic, Seung-Hwan Song
-
Patent number: 10026478Abstract: Systems and methods for improving the performance of a non-volatile memory array during a memory operation by concurrently applying two different selected word line voltages to two different word lines within the non-volatile memory array are described. The memory operation may comprise a write operation or a combination of SET and RESET operations. The memory array may include a first word line connected to a first set of memory cells, a second word line connected to a second set of memory cells, and a third word line connected to a third set of memory cells. During the memory operation, the first word line may be set to a first selected word line voltage (e.g., 3V), the second word line may be set to a second selected word line voltage (e.g., 0V), and the third word line may be set to an unselected word line voltage (e.g., 1.5V).Type: GrantFiled: March 3, 2017Date of Patent: July 17, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Won Ho Choi, Jay Kumar, Zvonimir Bandic
-
Publication number: 20180197607Abstract: A first write operation is received. The first write operation includes a SET operation. The SET operation is configured to place a cell of the non-volatile memory (NVM) device in a relatively low-resistance state. A second write operation is received. A first electrical pulse is applied to a first cell of the NVM device. The first electrical pulse is applied to place the first cell in the relatively low-resistance state. A second electrical pulse is applied to a second cell of the NVM device. The second electrical pulse is applied before the first electrical pulse has concluded. The second cell and the first cell are both within a single tile of the NVM device.Type: ApplicationFiled: February 20, 2018Publication date: July 12, 2018Inventors: Zvonimir Z. BANDIC, Won Ho CHOI, Jay KUMAR
-
Publication number: 20180181465Abstract: The present disclosure generally relate to a device and method for ensuring error-free memory. Synchronized read and write flags generated by a memory portion are used to make a memory controller of a host portion free from error correction, read/write disturbance, wear leveling and any systematic read/write issues that may occur.Type: ApplicationFiled: December 22, 2016Publication date: June 28, 2018Inventors: Won Ho CHOI, Jay KUMAR, Kiran Kumar GUNNAM, Dejan VUCINIC, Zvonimir Z. BANDIC
-
Patent number: 9928907Abstract: A storage device includes a cross-point non-volatile memory (NVM) device that includes a first subset of cells. Cells of the first subset of cells may share either a bitline or a wordline. There may be at least one buffer cell on a respective bitline or wordline between each adjacent pair of cells from the first subset of cells. The storage device includes a control module. The control module is configured to receive a set of I/O operations. The control module is configured to execute a first subset of the set of I/O operations in parallel across the first subset of cells of the cross-point memory component. The control module may execute the first subset of the set of I/O operations such that I/O operations are not executed at the respective buffer cells.Type: GrantFiled: January 27, 2017Date of Patent: March 27, 2018Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Zvonimir Z. Bandic, Won Ho Choi, Jay Kumar
-
Patent number: 9911494Abstract: A storage device includes an interface, NVM device, and control module. The control module may be configured to receive a first write operation and a second write operation. The first write operation comprises a SET operation configured to place a cell of the NVM device in a relatively low-resistance state. The control module may be further configured to execute the first write operation by causing an electrical pulse to be applied to a first cell of the NVM device to place the first cell in the relatively low-resistance state. The control module may be further configured to execute the second write operation by causing an electrical pulse to be applied to a second cell of the NVM device before the first electrical pulse has concluded. A single tile of the NVM device includes the first cell and the second cell.Type: GrantFiled: January 11, 2017Date of Patent: March 6, 2018Assignee: Western Digital Technologies, Inc.Inventors: Zvonimir Z. Bandic, Won Ho Choi, Jay Kumar
-
Publication number: 20180061492Abstract: In an aspect of the disclosure, a method and an apparatus are provided. The apparatus may be a phase change memory (PCM). The PCM including, first and second phase change memory cells. The PCM including a bitline coupled to the first and the second phase change memory cells. The PCM including a memory controller configured to simultaneously write to the first and the second phase change memory cells by applying designated pulse waveforms to the bitline and wordlines.Type: ApplicationFiled: August 25, 2016Publication date: March 1, 2018Inventors: Won Ho Choi, Jay Kumar, Zvonimir Z. Bandic
-
Patent number: 8673159Abstract: Apparatus and methods for separating a fluid, with the apparatus including a rotatable drum having an inner drum wall and an outer drum wall disposed around the inner drum wall to define a separation passage therebetween. The apparatus also includes radial separator blades that are curved in a circumferential direction and are disposed in the separation passage of the drum, the radial separator blades extending radially at least partially between the inner drum wall and the outer drum wall. The apparatus further includes a first circumferential separator blade that is curved in a radial direction and is disposed in the separation passage of the drum, the first circumferential separator blade extending at least partially around the inner drum wall. The apparatus also includes a housing disposed around the drum and configured to receive a higher-density component of the fluid separated in the separation passage.Type: GrantFiled: June 28, 2011Date of Patent: March 18, 2014Assignee: Dresser-Rand CompanyInventors: Jay Kumar, H. Allan Kidd, William Maier
-
Publication number: 20130327725Abstract: Apparatus and methods for separating a fluid, with the apparatus including a rotatable drum having an inner drum wall and an outer drum wall disposed around the inner drum wall to define a separation passage therebetween. The apparatus also includes radial separator blades that are curved in a circumferential direction and are disposed in the separation passage of the drum, the radial separator blades extending radially at least partially between the inner drum wall and the outer drum wall. The apparatus further includes a first circumferential separator blade that is curved in a radial direction and is disposed in the separation passage of the drum, the first circumferential separator blade extending at least partially around the inner drum wall. The apparatus also includes a housing disposed around the drum and configured to receive a higher-density component of the fluid separated in the separation passage.Type: ApplicationFiled: June 28, 2011Publication date: December 12, 2013Applicant: DRESSER-RAND COMPANYInventors: Jay Kumar, Allan H. Kidd, William Maier
-
Publication number: 20130014755Abstract: An apparatus is provided for vaporizing a source of vaporizable substance for delivering an aerosol. The vaporizing apparatus comprises a housing defining a first combustion chamber, a second vaporizing chamber for receiving the vaporizable substance, and a transverse wall spanning the interior of the housing for separating the first chamber and the second chamber. A heat transfer element, comprising an elongated member of heat conductive material, extends from the first chamber through the wall and into the second chamber in heat transfer relation with the vaporizable substance for transferring heat from the first chamber to the vaporizable substance. A gas burner disposed in the combustion chamber converts fuel gas to a flame for heating the combustion chamber and the heat transfer element. The heat transfer element maintains the temperature in the second chamber at or above the vaporization temperature of the substance.Type: ApplicationFiled: July 11, 2012Publication date: January 17, 2013Inventors: Jay Kumar, Vikram Kumar
-
Publication number: 20110244826Abstract: A mobile communication plan offering system and method described herein determines one or more best-fit mobile communication plan offers for mobile communication device (“MCD”) users. Subscribers can also be referred to as “mobile subscribers” or “subscribers”. The mobile communication plan offers typically consist of one or more modifications to a plan (also referred to as packs) or a complete plan including a base plan plus a pack and are based on a mobile usage pattern of a subscriber. In at least one embodiment, the mobile communication plan offering system and method analyzes MCD usage behavior of a subscriber, processes the usage behavior and current spending of the subscriber, and determines a mobile communication plan offering that, if adopted, will result in a positive economic benefit to the subscriber compared with the subscriber's current plan.Type: ApplicationFiled: February 2, 2011Publication date: October 6, 2011Inventors: Subramaniyan Krishnan, Jay Kumar, Shankar Prasad
-
Patent number: 7499295Abstract: This invention generally relates to discontinuous conduction mode switch mode power supply (SMPS) controllers employing primary side sensing. We describe an SMPS controller which integrates a feedback signal from a point determined by a target operating voltage to a peak or trough of an oscillatory or resonant portion of the feedback signal when substantially no energy is being transferred to the SMPS output. When regulation is achieved this value should be zero; the difference from zero can be used to regulate the output voltage of the SMPS.Type: GrantFiled: June 7, 2007Date of Patent: March 3, 2009Assignee: Cambridge Semiconductor LimitedInventors: Mahesh Devarahandi Indika de Silva, Jay Kumar, Vinod A. Lalithambika
-
Publication number: 20080037294Abstract: This invention generally relates to discontinuous conduction mode switch mode power supply (SMPS) controllers employing primary side sensing. We describe an SMPS controller which integrates a feedback signal from a point determined by a target operating voltage to a peak or trough of an oscillatory or resonant portion of the feedback signal when substantially no energy is being transferred to the SMPS output. When regulation is achieved this value should be zero; the difference from zero can be used to regulate the output voltage of the SMPS.Type: ApplicationFiled: June 7, 2007Publication date: February 14, 2008Inventors: Mahesh Devarahandi Indika de Silva, Jay Kumar, Vinod A. Lalithambika
-
Patent number: 7248487Abstract: This invention generally relates to discontinuous conduction mode switch mode power supply (SMPS) controllers employing primary side sensing. We describe an SMPS controller which integrates a feedback signal from a point determined by a target operating voltage to a peak or trough of an oscillatory or resonant portion of the feedback signal when substantially no energy is being transferred to the SMPS output. When regulation is achieved this value should be zero; the difference from zero can be used to regulate the output voltage of the SMPS.Type: GrantFiled: June 1, 2006Date of Patent: July 24, 2007Assignee: Cambridge Semiconductor LimitedInventors: Mahesh Devarahandi Indika de Silva, Jay Kumar, Vinod A. Lalithambika