Abstract: Secure access and processing of an encryption/decryption key may include generating one or more keys within a key controller block of a chip. The generated keys may be transferred from the key controller block of the chip to an on-chip bus interface block via a secure serial link. The transferred keys may be stored in registers which may be accessible by only the key controller block of the chip. In this regard, the generated keys may be written to one or more of the key registers only by the key controller block. Furthermore, a written key may be read from a key register only by the key controller block. During the transfer of a generated key, a data valid signal may be used to indicate valid keys in a data signal used to transfer the keys via the secure serial link.

Abstract: System and method for generating and distributing an encryption/decryption key are disclosed and may include generating one or more keys by a key generator integrated within a chip. The generated one or more keys may be communicated directly from the key generator, via an on-chip broadcast serial link, to one of a plurality of on-chip addressable encryption/decryption devices. A particular one of the plurality of on-chip addressable encryption/decryption devices processes one or more received packets that include its own address utilizing the one or more keys. The at least one key may be serialized and encapsulated into a key packet. The encapsulating may include encapsulating an address of the one of the plurality of on-chip addressable encryption/decryption devices in the key packet.

Abstract: Controlling an encryption/decryption device using descriptors may include formatting a first block of memory to contain a generic data template used to control the encryption/decryption device. The first memory block may be configured with actual data values corresponding to the generic data template. At least a portion of the configured actual data values may be acquired and used for controlling one or more operations of the encryption/decryption device. A second memory block may be configured in a manner compatible with the first memory block format. The second memory block may also be configured with actual data values corresponding to the generic data template of first block of memory. The second block of memory may be linked to the first memory block. The first and second block of memory may be a random access memory.

Abstract: System and method for generating and distributing an encryption/decryption key are disclosed and may include generating one or more keys by a key generator integrated within a chip. The generated one or more keys may be communicated directly from the key generator, via an on-chip broadcast serial link, to one of a plurality of on-chip addressable encryption/decryption devices. A particular one of the plurality of on-chip addressable encryption/decryption devices processes one or more received packets that include its own address utilizing the one or more keys. The at least one key may be serialized and encapsulated into a key packet. The encapsulating may include encapsulating an address of the one of the plurality of on-chip addressable encryption/decryption devices in the key packet.

Abstract: Aspects of an encryption/decryption key generation and distribution may include generating one or more keys for use by one of a plurality of encryption/decryption devices coupled to a serial link within a chip. The generated keys may be transmitted via, for example, a high speed serial link to which one or more of the encryption/decryption devices in the chip may be coupled. The encryption/decryption devices coupled to the serial link may be adapted to examine or identify the transmitted key packets on the serial link and determine whether a particular key packet contains a key that which should be utilized by a particular one of the encryption/decryption devices. Upon identification of a key, the key may subsequently be processed and/or utilized by an integrated encryption/decryption processor associated with the encryption/decryption device to which the encryption key belongs.

Abstract: An aspect of the of the invention may include the transfer of a block of data from a first memory location to a second memory location in a DRAM. During the transfer of the block of data from the first memory location, if an encryption mode is selected, the data may be buffered, encrypted, and then stored in the second memory location. If a decryption mode is selected, the transferred data may be buffered, decrypted and then stored in the second memory location. If a bypass mode is selected, the data may be buffered and then stored in the second memory location. In this regard, the encryption/decryption operations may be bypassed.

Abstract: An aspect of the of the invention may include the transfer of a block of data from a first memory location to a second memory location in a DRAM. During the transfer of the block of data from the first memory location, if an encryption mode is selected, the data may be buffered, encrypted, and then stored in the second memory location. If a decryption mode is selected, the transferred data may be buffered, decrypted and then stored in the second memory location. If a bypass mode is selected, the data may be buffered and then stored in the second memory location. In this regard, the encryption/decryption operations may be bypassed.

Abstract: Secure access and processing of an encryption/decryption key may include generating one or more keys within a key controller block of a chip. The generated keys may be transferred from the key controller block of the chip to an on-chip bus interface block via a secure serial link. The transferred keys may be stored in registers which may be accessible by only the key controller block of the chip. In this regard, the generated keys may be written to one or more of the key registers only by the key controller block. Furthermore, a written key may be read from a key register only by the key controller block. During the transfer of a generated key, a data valid signal may be used to indicate valid keys in a data signal used to transfer the keys via the secure serial link.

Abstract: Aspects of an encryption/decryption key generation and distribution may include generating one or more keys for use by one of a plurality of encryption/decryption devices coupled to a serial link within a chip. The generated keys may be transmitted via, for example, a high speed serial link to which one or more of the encryption/decryption devices in the chip may be coupled. The encryption/decryption devices coupled to the serial link may be adapted to examine or identify the transmitted key packets on the serial link and determine whether a particular key packet contains a key that which should be utilized by a particular one of the encryption/decryption devices. Upon identification of a key, the key may subsequently be processed and/or utilized by an integrated encryption/decryption processor associated with the encryption/decryption device to which the encryption key belongs.

Abstract: Controlling an encryption/decryption device using descriptors may include formatting a first block of memory to contain a generic data template used to control the encryption/decryption device. The first memory bock may be configured with actual data values corresponding to the generic data template. At least a portion of the configured actual data values may be acquired and used for controlling one or more operations of the encryption/decryption device. A second memory block may be configured in a manner compatible with the first memory block format. The second memory block may also be configured with actual data values corresponding to the generic data template of first block of memory. The second block of memory may be linked to the first memory block. The first and second block of memory may be a random access memory.