Abstract: An interface circuit is used to permit a data multiplexing circuit to receive data from two channels which are asynchronously clocked. The data from the two channels is received by the interface circuit and transferred to the multiplexing circuit in a manner determined by clock signals.

Abstract: An electronic device, such as a bubble memory (21), which has a narrow temperature band of operation, is maintained within the narrow temperature band by a Peltier circuit (30). The Peltier circuit (30) includes a Peltier junction (31) which is placed in a heat conducting relationship with the bubble memory (21). The Peltier circuit (30) has the advantage of being able to alternately heat or chill the bubble memory device (21) in order to maintain the bubble memory device (21) within its recommended temperature range.

Abstract: A tester determines a system failure by employing an error detector (28, 30, 31; 40, 42, 44, 46) coupled to the plurality of output lines from a strobing circuit (10, 12, 14, 16, 18). This strobing circuit normally generates a singular signal on one of these plurality of lines. The error detector (28, 30, 32; 40, 42, 44, 46) responds to a singular signal being produced on two of the plurality of lines by producing an error signal. Thus, in the preferred embodiment a performance check can be performed on a significant number of internal digital lines by monitoring a single line which may be routed to an external connector.

Abstract: A portable multiplex bus exerciser for exercising any digital communications multiplex bus having a system under test which is of the command/response type. A command word and an optional data word, programmable as to address, message length, and data content, are applied to either of two multiplex buses. By examining the activity of a bus line (or lines) the responses of the system under test can be analyzed to determine its operational readiness.

Abstract: In a system of the type including means for transmitting differential digital input signals and means for receiving the transmitted signals, apparatus associated with the system for programming the inputs to and thereby controlling the operational outputs from the receiving means, whereby a self-test capability is imparted to the system.

Abstract: A biphase waveform is generated using a serial register of length 2N where N is the number of bits to be transmitted. Each data bit is loaded into a shift register, both directly and through an inverter. Double speed clocking provides an alternating logic level signal for each data bit and the phases of the alternating signals are combined to provide the biphase waveform.