Abstract: A digital video communication device is provided. The digital video communication device includes a transmitter providing a spread-spectrum video signal including a predetermined frequency spread value and a frequency ratio and a receiver receiving the spread-spectrum video signal. The receiver includes a frequency synthesizer, a free-running clock generator configured to generate a free-running clock signal, wherein the free-running clock signal is used as a reference clock signal input to the frequency synthesizer. The receiver further includes a digital control logic circuit configured to separate the frequency ratio from the spread-spectrum video signal, and a line buffer coupled to the digital control logic circuit and the frequency synthesizer, the line buffer adjusting the frequency ratio and sending the adjusted frequency ratio to the frequency synthesizer, wherein the frequency synthesizer combines the free-running clock signal and the adjusted frequency ratio, and outputs a de-spread clock signal.

Abstract: A digital video communication device is provided. The digital video communication device includes a transmitter providing a spread-spectrum video signal including a predetermined frequency spread value and a frequency ratio and a receiver receiving the spread-spectrum video signal. The receiver includes a frequency synthesizer, a free-running clock generator configured to generate a free-running clock signal, wherein the free-running clock signal is used as a reference clock signal input to the frequency synthesizer. The receiver further includes a digital control logic circuit configured to separate the frequency ratio from the spread-spectrum video signal, and a line buffer coupled to the digital control logic circuit and the frequency synthesizer, the line buffer adjusting the frequency ratio and sending the adjusted frequency ratio to the frequency synthesizer, wherein the frequency synthesizer combines the free-running clock signal and the adjusted frequency ratio, and outputs a de-spread clock signal.

Abstract: System and method for implementing a self-adjusting audio clock in an audio receiver comprising an audio data buffer for buffering data received from a transmitter are described. In one embodiment, the system includes an audio clock recovery circuit for recovering an audio clock signal from a reference clock signal received from the transmitter, wherein the audio clock is provided to the audio data buffer for use in reading data therefrom. The system further includes an adjustment circuit for providing an adjustment signal to the audio clock recovery circuit in accordance with a status of the audio data buffer. Responsive to the status of the audio data buffer indicating that the audio data buffer is approaching overflow, the adjustment signal provided to the audio clock recovery circuit causes an increase in the frequency of the audio clock signal.

Abstract: A method to provide 3D video display includes the steps of receiving 3D information from the auxiliary channel corresponding to a frame; and providing the 3D information to a user accessory having stereoscopic capabilities so that the user accessory operate according to the 3D information when the frame is displayed. Further provided is a video system to provide 3D video displays including a receiver to receive the 3D information corresponding to a frame from the auxiliary channel in a transmission link, and to provide the 3D information to a user accessory as the frame is displayed. A 3D video display setup is also provided including a video system as above; a receiver having a display; and a clock to synchronize the display with a user accessory; and a user accessory having stereoscopic capabilities.