Abstract: Methods and apparatus for implementing and operating one or more pseudo-synchronous registers with reduced power consumption, and reduced complexity for transferring data between clock domains. Various embodiments of the present invention replace conventional continuous clocking schemes with a strobe signal that is only generated when a data transfer operation with the one or more pseudo-synchronous registers is to take place. The strobe signal is generated so as to have a duration of one full cycle of the clock signal which defines the clock domain in which the at least one pseudo-synchronous register resides.

Abstract: A computer system including a host CPU, a primary PCI bus coupled to the CPU, and a bus adapter coupled to the primary PCI bus, wherein the host CPU can access peripherals comprised in the bus adapter even when the bus adapter is inoperable. The bus adapter includes a PCI to PCI interface controller which includes a primary PCI interface for coupling to the primary PCI bus and a secondary PCI interface bridge for coupling to a secondary PCI bus. Peripheral bus interface logic is coupled between the primary PCI interface and the secondary PCI interface, and this interface logic couples to various peripheral devices, including ROM/Flash memory and non-volatile static random access memory (NVSRAM). According to the present invention, a host utility executing on the CPU can access the peripheral devices without having to access the secondary PCI bus.

Abstract: A SCSI controller card which includes a standard SCSI connector that can support either one or two SCSI channels, as desired. The connector can receive either a standard single channel cable or a specially designed dual channel "Y" cable to provide either one or two SCSI channels, respectively. The SCSI controller card includes logic that determines which cable is installed and switching logic which routes one or two SCSI channels to the connector accordingly. In the preferred embodiment, the SCSI adapter card includes two SCSI controllers which provide two SCSI channels. A first channel is connected directly to pins on the SCSI connector. A second channel is connected to switching logic, and a plurality of ground signals are also connected to the switching logic. The second channel is switched into the SCSI connector if the dual channel "Y" cable is attached to the connector, and the ground signals are switched into the SCSI connector if the "Y" cable is not detected.

Abstract: A computer system including a host CPU, a primary PCI bus coupled to the CPU, and a bus adapter coupled to the primary PCI bus, wherein the host CPU can access peripherals comprised in the bus adapter even when the bus adapter is inoperable. The bus adapter includes a PCI to PCI interface controller which includes a primary PCI interface for coupling to the primary PCI bus and a secondary PCI interface bridge for coupling to a secondary PCI bus. Peripheral bus interface logic is coupled between the primary PCI interface and the secondary PCI interface, and this interface logic couples to various peripheral devices, including ROM/Flash memory and non-volatile static random access memory (NVSRAM). According to the present invention, a host utility executing on the CPU can access the peripheral devices without having to access the secondary PCI bus.

Abstract: A SCSI adapter card which provides one or more internal SCSI channels and includes connectors for an optional daughter card which provides an external SCSI connector. The daughter card is a parallel mezzanine style daughter board which provides modular and upgradable SCSI bus routing options. In the preferred embodiment, the adapter card includes two SCSI controllers which provide two internal SCSI channels. The daughter board can include up to 2 SCSI controllers for additional SCSI channels. The daughter board can reroute one or more of the internal SCSI channels to the external connector according to various SCSI routing options or can include one or more SCSI controllers for additional SCSI channels. In one embodiment, the daughter board does not include a SCSI controller, but rather serves to reroute one or more of the internal SCSI controllers to the external connector.

Abstract: A peripheral resource controller such as a caching disk array controller is provided for controlling the transfer of data between a host bus and a peripheral resource, such as an array of hard disk drives. The peripheral resource controller includes a bus interface controller for providing an interface between the host bus and a local bus of the peripheral controller. The bus interface controller further includes a peripheral bus interface which accommodates accesses to a peripheral bus and a DMA controller for controlling direct memory access operations between a local memory of the peripheral controller and a system memory of the host computer. A DMA transfer list memory is coupled to the peripheral bus for storing DMA transfer information. The DMA controller fetches host and local address as well as block size information from the DMA transfer list memory to thereby effectuate DMA operations.