Abstract: A compatibility is ascertained between a configuration of a quantum processor (q-processor) of a quantum cloud compute node (QCCN) in a quantum cloud environment (QCE) and an operation requested in a first instruction in a portion (q-portion) of a job submitted to the QCE, the QCE including the QCCN and a conventional compute node (CCN), the CCN including a conventional processor configured for binary computations. In response to the ascertaining, a quantum instruction (q-instruction) is constructed corresponding to the first instruction. The q-instruction is executed using the q-processor of the QCCN to produce a quantum output signal (q-signal). The q-signal is transformed into a corresponding quantum computing result (q-result). A final result is returned to a submitting system that submitted the job, wherein the final result comprises the q-result.

Abstract: According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise an extrapolation component that extrapolates a system parameter of a parameter set to determine a starting parameter value of a variational circuit. The computer executable components can further comprise a variational component that determines a system parameter value of the parameter set based on the starting parameter value.

Abstract: Lattice arrangements for quantum qubits are described. A lattice arrangement can comprise adjacent structures having vertices connected by edges. The qubits can be positioned on the vertices. A qubit in the lattice arrangement directly connects to not more than three other qubits, or connects to another qubit via a coupling qubit on an edge between two qubits on a vertex. The adjacent structures can comprise hexagons, dodecagons or octagons. A superconducting qubit lattice can comprise superconducting target qubits and superconducting control qubits. The superconducting qubit lattice can comprise adjacent structures having vertices connected by edges, with target qubits positioned on the vertices and control qubits positioned on the edges. Logic operations between adjacent superconducting target and control qubits can be implemented by driving the superconducting control qubit at or near the frequency of the superconducting target qubit.

Abstract: A method for validation and runtime estimation of a quantum algorithm includes receiving a quantum algorithm and simulating the quantum algorithm, the quantum algorithm forming a set of quantum gates. The method further includes analyzing a first set of parameters of the set of quantum gates and analyzing a second set of parameters of a set of qubits performing the set of quantum gates. The method further includes transforming, in response to determining at least one of the first set of parameters or the second set of parameters meets an acceptability criterion, the quantum algorithm into a second set of quantum gates.

Abstract: A quantum computer includes a quantum processor that includes a first plurality of qubits arranged in a hexagonal lattice pattern such that each is substantially located at a hexagon apex, and a second plurality of qubits each arranged substantially along a hexagon edge. Each of the first plurality of qubits is coupled to three nearest-neighbor qubits of the second plurality of qubits, and each of the second plurality of qubits is coupled to two nearest-neighbor qubits of the first plurality of qubits. Each of the second plurality of qubits is a control qubit at a control frequency. Each of the first plurality of qubits is a target qubit at one of a first target frequency or a second target frequency. The quantum computer includes an error correction device configured to operate on the hexagonal lattice pattern of the plurality of qubits so as to detect and correct data errors.

Abstract: Techniques and a system for quantum computing device modeling and design are provided. In one example, a system includes a modeling component and a simulation component. The modeling component models a quantum device element of a quantum computing device as an electromagnetic circuit element to generate electromagnetic circuit data for the quantum computing device. The simulation component simulates the quantum computing device using the electromagnetic circuit data to generate response function data indicative of a response function for the quantum computing device. Additionally or alternatively, a Hamiltonian is constructed based on the response function.

Abstract: A repository is configured in a hybrid data processing environment comprising a classical computing system and a quantum computing system, to hold a plurality of quantum circuit components (QCC(s)). A degree of difficulty in simulating the received QCC in the classical computing system is transformed into a classical hardness score. A degree of difficulty in implementing the received QCC in the quantum computing system is transformed into a quantum hardness score. A first parameter in a metadata data structure associated with the received QCC is populated with the classical hardness score. A second parameter in the metadata data structure associated with the received QCC is populated with the quantum hardness score. The received QCC is transformed into a library element by at least augmenting the received QCC with the metadata data structure. The library element is added to the repository.

Abstract: A method of mitigating quantum readout errors by stochastic matrix inversion includes performing a plurality of quantum measurements on a plurality of qubits having predetermined plurality of states to obtain a plurality of measurement outputs; selecting a model for a matrix linking the predetermined plurality of states to the plurality of measurement outputs, the model having a plurality of model parameters, wherein a number of the plurality of model parameters grows less than exponentially with a number of the plurality of qubits; training the model parameters to minimize a loss function that compares predictions of the model with the matrix; computing an inverse of the model based on the trained model parameters; and providing the computed inverse of the model to a noise prone quantum readout of the plurality of qubits to obtain a substantially noise free quantum readout.

Abstract: A method includes measuring an amplitude of a state of a quantum circuit, the amplitude corresponding to a first location in an object database. In the embodiment, the method includes executing, using a classical processor and a first memory, a verification operation, responsive to measuring the amplitude, to verify a target object in the first location. In the embodiment, the method includes re-measuring a second amplitude of a second state of the quantum circuit, the second amplitude having undergone a first plurality of amplitude amplifications, the second amplitude corresponding to a second location in the object database, the second location being verified as the target object, and wherein a total number of the first plurality of amplitude amplifications being less than a square root of a set of objects in the object database.

Abstract: A method of mitigating quantum readout errors by stochastic matrix inversion includes performing a plurality of quantum measurements on a plurality of qubits having predetermined plurality of states to obtain a plurality of measurement outputs; selecting a model for a matrix linking the predetermined plurality of states to the plurality of measurement outputs, the model having a plurality of model parameters, wherein a number of the plurality of model parameters grows less than exponentially with a number of the plurality of qubits; training the model parameters to minimize a loss function that compares predictions of the model with the matrix; computing an inverse of the model based on the trained model parameters; and providing the computed inverse of the model to a noise prone quantum readout of the plurality of qubits to obtain a substantially noise free quantum readout.

Abstract: A method for validation and runtime estimation of a quantum algorithm includes receiving a quantum algorithm and simulating the quantum algorithm, the quantum algorithm forming a set of quantum gates. The method further includes analyzing a first set of parameters of the set of quantum gates and analyzing a second set of parameters of a set of qubits performing the set of quantum gates. The method further includes transforming, in response to determining at least one of the first set of parameters or the second set of parameters meets an acceptability criterion, the quantum algorithm into a second set of quantum gates.

Abstract: In an embodiment, a method includes measuring a first number of control qubits in a quantum algorithm, wherein a quantum circuit representation of the quantum algorithm includes a multiple-controlled-NOT gate. In an embodiment, a method includes measuring a second number of ancilla qubits in a quantum computer. In an embodiment, a method includes comparing the first number and the second number to determine an optimum compilation method for a quantum circuit. In an embodiment, a method includes compiling, in response to the comparison determining the second number is greater than one and less than the difference of the first number and 2, a quantum circuit from the quantum algorithm using a hybrid method.

Abstract: Techniques for facilitating reduced thermal resistance attenuator on high-thermal conductivity substrates for quantum applications are provided. A device can comprise a substrate that provides a thermal conductivity level that is more than a defined thermal conductivity level. The device can also comprise one or more grooved transmission lines formed in the substrate. The one or more grooved transmission lines can comprise a powder substance. Further, the device can comprise one or more copper heat sinks formed in the substrate. The one or more copper heat sinks can provide a ground connection. Further, the one or more copper heat sinks can be formed adjacent to the one or more grooved transmission lines.

Abstract: The illustrative embodiments provide a method, system, and computer program product for quantum feature kernel alignment using a hybrid classical-quantum computing system. An embodiment of a method for hybrid classical-quantum decision maker training includes receiving a training data set. In an embodiment, the method includes selecting, by a first processor, a sampling of objects from the training set, each object represented by at least one vector. In an embodiment, the method includes applying, by a quantum processor, a set of quantum feature maps to the selected objects, the set of quantum maps corresponding to a set of quantum kernels. In an embodiment, the method includes evaluating, by a quantum processor, a set of parameters for a quantum feature map circuit corresponding to at least one of the set of quantum feature maps.

Abstract: Techniques for facilitating quantum pulse optimization using machine learning are provided. In one example, a system includes a classical processor and a quantum processor. The classical processor employs a quantum pulse optimizer to generate a quantum pulse based on a machine learning technique associated with one or more quantum computing processes. The quantum processor executes a quantum computing process based on the quantum pulse.

Abstract: A quantum computing device including a first plurality of qubits having a first resonance frequency and a second qubit having a second resonance frequency, the second resonance frequency being different from the first resonance frequency; and a first tunable frequency bus configured to couple the first plurality of qubits to the second qubit.

Abstract: A quantum computer includes a quantum processor that includes a first plurality of qubits arranged in a hexagonal lattice pattern such that each is substantially located at a hexagon apex, and a second plurality of qubits each arranged substantially along a hexagon edge. Each of the first plurality of qubits is coupled to three nearest-neighbor qubits of the second plurality of qubits, and each of the second plurality of qubits is coupled to two nearest-neighbor qubits of the first plurality of qubits. Each of the second plurality of qubits is a control qubit at a control frequency. Each of the first plurality of qubits is a target qubit at one of a first target frequency or a second target frequency. The quantum computer includes an error correction device configured to operate on the hexagonal lattice pattern of the plurality of qubits so as to detect and correct data errors.

Abstract: A superconducting coupling device includes a resonator structure. The resonator structure has a first end configured to be coupled to a first device and a second end configured to be coupled to a second device. The device further includes an electron system coupled to the resonator structure, and a gate positioned proximal to a portion of the electron system. The electron system and the gate are configured to interrupt the resonator structure at one or more predetermined locations forming a switch. The gate is configured to receive a gate voltage and vary an inductance of the electron system based upon the gate voltage. The varying of the inductance induces the resonator structure to vary a strength of coupling between the first device and the second device.

Abstract: A method includes detecting submission of a first quantum circuit for compilation, the first quantum circuit comprising a first set of quantum logic gates; generating a first gate index, the first gate index comprising an ordered table of a subset of the set of quantum logic gates, each quantum logic gate of the subset of quantum logic gates including a corresponding set of qubits acted on by the quantum logic gate; comparing the first gate index with a second gate index to determine a structural equality of the first quantum circuit and the second quantum circuit; and parameterizing, in response to determining a structural equality of the first quantum circuit and the second quantum circuit, a first set of parameters of a second set of quantum logic gates of the second quantum circuit with a second set of parameters of the first set of quantum logic gates.

Abstract: A quantum computing device including a first plurality of qubits having a first resonance frequency and a second qubit having a second resonance frequency, the second resonance frequency being different from the first resonance frequency; and a first tunable frequency bus configured to couple the first plurality of qubits to the second qubit.