Abstract: A modified flow for ASIC place an route software flow which allows incorporation into the flow, a process for tracking the locations of substrate contacts and well-ties within and outside the boundaries of placed cells and generating required supplemental placements, making possible an efficient use of silicon chip area expended in the adequate placement of substrate contacts and well-ties.

Abstract: A process variance detection technique for detecting fabrication processing variances in integrated circuit components, such as resistors or MOSFETs, is based on the decreased sensitivity to processing variations exhibited by components that are up-sized relative to similar components with nominal dimensions. Detection circuitry includes detection components with both nominal and up-sized dimensions, and variance detection involves detecting the differences in operational response of the nominal and up-sized detection components. For bipolar logic, resistors are fabricated with up-sized widths, while for MOS logic, MOSFETs are fabricated with up-sized gate lengths.

Abstract: A flip-flop having a master section including two switching transistors is provided with output loading transistors to drive the two transistors into saturation in the event of a metastable condition causing input is present. By driving the switching transistors into saturation they become inactive and background noise cannot cause proprogation of the metastable condition to subsequent flip-flip stages.

Abstract: A synchronized pulsed look-ahead circuit (10 in FIG. 1) effects look-ahead operations for a flip-flop (20). It includes a LAPP section (12) and a DATA sense and control section (14). To initiate a look-ahead operation, the LAPP section triggers in synchronism with the control edge of CLK, swtiching the LAPP line active and enabling the DATA sense and control section. While enabled, the DATA sense and control section receives DATA IN, and depending on its phase, provides the appropriate logic levels to the DATA output driver, which then provides the appropriate DATA OUT. When the flip-flop has latched the DATA and is ready to assume control of the DATA OUT line, i.e., after the associated propagation delay, the LAPP pulse is terminated and the DATA sense and control section is disabled, terminating the look-ahead operation.

Abstract: A flip-flop has a master section (74) comprising two transistors (40, 48). The second transistor (48) has two emitters, the second emitter conducting in response to a metastable condition wherein both transistors (40,48) are conducting concurrently, resulting in a metastable output. The second emitter (76) draws additional current through the second transistor (48) after a delay provided by a second clock (78), thus disrupting the equilibrium of the master section (74). By drawing additional current, the second transistor (48) will turn the first transistor (40) off, enabling a valid output.