Abstract: In one embodiment, a processor includes: at least one domain to operate at an independent voltage and frequency and including a monitor circuit; and a power controller to control power consumption of the at least one domain and to control the monitor circuit to monitor an operating voltage of the at least one domain during active operation of the at least one domain and to prevent the monitor circuit from the monitoring of the operating voltage when the at least one domain is inactive. Other embodiments are described and claimed.

Abstract: Training of a link is performed, wherein the link is an interconnect between two devices of a computer system. A built-in self-test (BIST) of the link is performed. A result from the link training is compared to a result from the BIST. A link status of the link is posted, wherein the link status is based at least in part on the result from the link training and the result from the BIST.

Abstract: Methods and apparatus for performing a data driven test on a circuit including at least one built-in-self-test compatible device. In one embodiment, the method includes describing the device using a descriptive language including setting at least one default value associated with the device. The method also includes defining a scan path associated with the device, defining a netlist of the circuit, and configuring a test control program for the circuit. Additionally, the method includes changing the default value associated with the device. Testing the circuit after changing the value and using the test control program is also included wherein a portion of the test control program associated with the value remains substantially unmodified.

Abstract: A graphic user interface for configuring a test control program for a circuit. More particularly the circuit includes a built-in-self-test compatible device and has a test configuration. The device has an associated value. Moreover, the circuit, the device, and the value are defined in a circuit definition. The interface includes an object representing the circuit, an object representing the device, and an object representing the value. Furthermore, at least one of the objects is configured and adapted to allow a modification to the object and to reconfigure the test configuration program in response to the object modification. Also, the object is further configured and adapted to modify itself to reflect a modification of the circuit definition. More particularly, the device may be an IBIST compatible device having registers, ports and lanes of the ports. Methods of, and computer programs for, configuring test control programs are also provided.

Abstract: Training of a link is performed, wherein the link is an interconnect between two devices of a computer system. A built-in self-test (BIST) of the link is performed. A result from the link training is compared to a result from the BIST. A link status of the link is posted, wherein the link status is based at least in part on the result from the link training and the result from the BIST.

Abstract: A methodology for testing a computer system using multiple test units, each test unit being associated with its respective core function circuitry. The core circuitry and its respective test unit are located in a primary integrated circuit component of the computer system, such as a processor, memory, or chipset. The on-chip test units communicate with one another and with other parts of the system, to determine whether a specification of the computer system is satisfied, without requiring a processor core of the computer system to execute an operating system program for the computer system.

Abstract: A built-in self test (IBIST) architecture/methodology is provided for testing the functionality of an interconnect (such as a bus) between two components. This IBIST architecture may include a pattern generator and a pattern checker. The pattern checker operates to compare a received plurality of bits (for the pattern generator) with a previously stored plurality of bits.

Abstract: In some embodiments, built-in self-test logic is provided for an integrated circuit (IC) device having memory controller logic to generate address and command information for accessing a memory device. Driver circuits are on-chip with the memory controller logic. The driver circuits have outputs that are coupled to on-chip signal pads, respectively. The BIST logic is coupled between the driver circuits and the controller logic. The BIST logic is to transmit, at speed, address and command information that has been generated by the controller logic using the driver circuits in a normal mode of operation for the device. In addition, the BIST logic is able to transmit, at speed, test symbols using the driver circuits in a test mode of operation for the IC device, during which a chip-to-chip connection between the IC device and another device is tested. Other embodiments are also described and claimed.

Abstract: In some embodiments, built-in self-test logic is provided for an integrated circuit (IC) device having memory controller logic to generate address and command information for accessing a memory device. Driver circuits are on-chip with the memory controller logic. The driver circuits have outputs that are coupled to on-chip signal pads, respectively. The BIST logic is coupled between the driver circuits and the controller logic. The BIST logic is to transmit, at speed, address and command information that has been generated by the controller logic using the driver circuits in a normal mode of operation for the device. In addition, the BIST logic is able to transmit, at speed, test symbols using the driver circuits in a test mode of operation for the IC device, during which a chip-to-chip connection between the IC device and another device is tested. Other embodiments are also described and claimed.

Abstract: A methodology for testing a computer system using multiple test units, each test unit being associated with its respective core function circuitry. The core circuitry and its respective test unit are located in a primary integrated circuit component of the computer system, such as a processor, memory, or chipset. The on-chip test units communicate with one another and with other parts of the system, to determine whether a specification of the computer system is satisfied, without requiring a processor core of the computer system to execute an operating system program for the computer system.

Abstract: A built-in self test (IBIST) architecture/methodology is provided for testing the functionality of an interconnect (such as a bus) between two components. This IBIST architecture may include a pattern generator and a pattern checker. The pattern checker operates to compare a received plurality of bits (for the pattern generator) with a previously stored plurality of bits.