Abstract: Techniques are disclosed for the use of fused vector processor instructions by a vector processor architecture. Each fused vector processor instruction may include a set of fields associated with individual vector processing instructions. The vector processor architecture may implement local buffers facilitating a single vector processor instruction to be used to execute each of the individual vector processing instructions without re-accessing vector registers between each executed individual vector processing instruction. The vector processor architecture enables less communication across the interconnection network, thereby increasing interconnection network bandwidth and the speed of computations, and decreasing power usage.

Abstract: Systems, methods, and apparatuses relating to vector processor architecture having an array of identical circuit blocks are described.

Abstract: Systems, methods, and apparatuses relating to vector processor architecture having an array of identical circuit blocks are described.

Abstract: A multi-channel serializing/deserializing (“serdes”) receiver, a method of operating the receiver and an integrated circuit configured as a serdes receiver. In one embodiment, the receiver includes:(1) a central frequency synthesizer configured to provide both in-phase and quadrature-phase clock signals and (2) a plurality of channel-specific receivers coupled to the central frequency synthesizer. Each of the plurality of channel-specific receivers is configured to receive and deserialize a data signal and include a clock recovery circuit having a phase detector and a phase interpolator. The interpolator is configured to receive the clock signals from the central frequency synthesizer and couple the phase detector and the central frequency synthesizer.

Abstract: A multi-channel serializing/deserializing (“serdes”) receiver, a method of operating the receiver and an integrated circuit configured as a serdes receiver. In one embodiment, the receiver includes:(1) a central frequency synthesizer configured to provide both in-phase and quadrature-phase clock signals and (2) a plurality of channel-specific receivers coupled to the central frequency synthesizer. Each of the plurality of channel-specific receivers is configured to receive and deserialize a data signal and include a clock recovery circuit having a phase detector and a phase interpolator. The interpolator is configured to receive the clock signals from the central frequency synthesizer and couple the phase detector and the central frequency synthesizer.

Abstract: A multi-channel serializing/deserializing (“serdes”) receiver, a method of operating the receiver and an integrated circuit configured as a serdes receiver. In one embodiment, the receiver includes: (1) a PLL-based central frequency synthesizer and (2) a plurality of channel-specific receivers coupled to the central frequency synthesizer, each of the plurality including a clock recovery system having a phase detector and a phase interpolator, the clock recovery system coupling the phase detector and the central frequency synthesizer.

Abstract: A multi-channel serializing/deserializing (“serdes”) receiver, a method of operating the receiver and an integrated circuit configured as a serdes receiver. In one embodiment, the receiver includes: (1) a PLL-based central frequency synthesizer and (2) a plurality of channel-specific receivers coupled to the central frequency synthesizer, each of the plurality including a clock recovery system having a phase detector and a phase interpolator, the clock recovery system coupling the phase detector and the central frequency synthesizer.