Abstract: A shift register having a first bistable latching circuit operable for switching between a low voltage state and a high voltage state in response to receiving an input current and a first clock voltage pulse. A second bistable latching circuit operable for switching from said low voltage state to the high voltage state in response to receiving a switching current induced from the first bistable latching circuit and a second clock voltage pulse. A clock voltage pulse source operable for successively providing clock voltage pulses in phase sequence to the first and second bistable latching circuits.

Abstract: The variable Gaussian convolution of an optical image is performed using a transparency, a focusing lens, a TV camera and a mechanism which moves the camera. The transparency has pattern inscribed on it which diffracts the light of the image with a Gaussian function of radius. The focusing lens receives the diffracted image from the transparency and focuses it. The camera receives the Gaussian convolution of the optical image from the focusing lens by being initially positioned along the optical axis of the lens at the focal length of the lens. As the camera is shifted to variable positions by the mechanism, the size of the Gaussian function increases as the camera is moved towards the lens, and is decreased as the camera is moved away from the lens.

Abstract: A Gaussian convolution is produced in a CCD imager or shift register by a method involving a special clocking sequence. The principle of operation, analagous to the process of diffusion, involves the deliberate intermixing of adjacent charge packets in a controlled way. Amounts of charge are exchanged between adjacent pixels a number of times, the result approximating the convolution of the image with a Gaussian function whose width is dependent upon the number of mixing cycles.

Abstract: A signal processor having a plurality of charge transfer devices adapted for coupling to an input signal source. Each one of such devices produces a sample of the input signal in response to a sampling signal. An input shift register having a plurality of serially coupled stages is provided, each one of such stages being coupled to a corresponding one of the charge transfer devices. Circuitry is included for enabling the sampling signal to be sequentially produced at an output of each one of the serially coupled stages, enabling sequential samples of the input signal to be produced in corresponding ones of the charge transfer devices.

Abstract: A charge transfer device having a source diffusion region, an isolation gate region, a reference voltage gate region and an input signal gate region disposed contiguously along such device, the isolation gate region being adapted for coupling to a pulse voltage source, the duration of such pulse being related to a predetermined sampling interval (and therefore related to the bandwidth of an input signal being sampled), the reference voltage gate region being adapted for coupling to a reference voltage source and the input signal gate region being adapted for coupling to the input signal. During each clock interval prior to the sampling interval the source diffusion region is pulsed, thereby enabling charge to pass from such region into the reference voltage gate region and the input gate region.

Abstract: A method of storing electric charges in a metal-nitride-oxide-semiconductor memory element by setting the threshold voltage of the element at any of a substantial number of voltages by applying both a DC voltage corresponding to the analog voltage to be stored and an AC voltage which is gradually reduced.