Patents by Inventor Jay Parks

Jay Parks has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Vertically-oriented semiconductor selection device providing high drive current in cross-point array memory
    Patent number: 8723252
    Abstract: A vertical semiconductor material mesa upstanding from a semiconductor base that forms a conductive channel between first and second doped regions. The first doped region is electrically coupled to one or more first silicide layers on the surface of the base. The second doped region is electrically coupled to one of a plurality of second silicide layers on the upper surface of the mesa. A gate conductor is provided on one or more sidewalls of the mesa.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: May 13, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej Sandhu, John K. Zahurak, Jay Parks
  • Vertically-oriented semiconductor selection device providing high drive current in cross-point array memory
    Publication number: 20120326242
    Abstract: A vertical semiconductor material mesa upstanding from a semiconductor base that forms a conductive channel between first and second doped regions. The first doped region is electrically coupled to one or more first silicide layers on the surface of the base. The second doped region is electrically coupled to one of a plurality of second silicide layers on the upper surface of the mesa. A gate conductor is provided on one or more sidewalls of the mesa.
    Type: Application
    Filed: September 6, 2012
    Publication date: December 27, 2012
    Inventors: Gurtej Sandhu, John K. Zahurak, Jay Parks
  • Vertically-oriented semiconductor selection device providing high drive current in cross-point array memory
    Patent number: 8274110
    Abstract: A vertical semiconductor material mesa upstanding from a semiconductor base that forms a conductive channel between first and second doped regions. The first doped region is electrically coupled to one or more first silicide layers on the surface of the base. The second doped region is electrically coupled to one of a plurality of second silicide layers on the upper surface of the mesa. A gate conductor is provided on one or more sidewalls of the mesa.
    Type: Grant
    Filed: May 20, 2009
    Date of Patent: September 25, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej Sandhu, John K. Zahurak, Jay Parks
  • VERTICALLY-ORIENTED SEMICONDUCTOR SELECTION DEVICE PROVIDING HIGH DRIVE CURRENT IN CROSS-POINT ARRAY MEMORY
    Publication number: 20100295120
    Abstract: A vertical semiconductor material mesa upstanding from a semiconductor base that forms a conductive channel between first and second doped regions. The first doped region is electrically coupled to one or more first silicide layers on the surface of the base. The second doped region is electrically coupled to one of a plurality of second silicide layers on the upper surface of the mesa. A gate conductor is provided on one or more sidewalls of the mesa.
    Type: Application
    Filed: May 20, 2009
    Publication date: November 25, 2010
    Inventors: Gurtej Sandhu, John K. Zahurak, Jay Parks
  • Programming and evaluating through PMOS injection
    Publication number: 20060146617
    Abstract: A PMOS transistor includes a gate, drain, and source in a substrate and is isolated from adjacent transistors in the substrate by shallow trench isolation. The transistor is programmed by applying a gate voltage to the gate and generating a drain-to-source voltage across the transistor that is of sufficient magnitude such that electrons are injected into the shallow trench isolation. This degrades the transistor so that it cannot be turned off. In one embodiment, the magnitude of the source-to-drain voltage depends on the gate voltage.
    Type: Application
    Filed: March 1, 2006
    Publication date: July 6, 2006
    Inventor: Jay Parks
  • Programming and evaluating through PMOS injection
    Publication number: 20060028878
    Abstract: A PMOS transistor includes a gate, drain, and source in a substrate and is isolated from adjacent transistors in the substrate by shallow trench isolation. The transistor is programmed by applying a gate voltage to the gate and generating a drain-to-source voltage across the transistor that is of sufficient magnitude such that electrons are injected into the shallow trench isolation. This degrades the transistor so that it cannot be turned off. In one embodiment, the magnitude of the source-to-drain voltage depends on the gate voltage.
    Type: Application
    Filed: June 13, 2005
    Publication date: February 9, 2006
    Inventor: Jay Parks