Abstract: Techniques are disclosed for implementing software breakpoints in a processor system having at least one processor coupled to a main memory and associated with an instruction cache. A breakpoint code is inserted at a particular location in the instruction cache of at least a given one of the processors, and a control indicator associated with the particular location is set to a first state which allows the breakpoint code to be returned to the given processor from the instruction cache in response to a first fetch request directed to a corresponding address. Subsequently, the control indicator associated with the particular location is set to a second state which directs that a second fetch request to the corresponding address be serviced from the main memory. The control indicator state is then changed again after a determination has been made, from the control indicator having been set to the second state, that the second fetch request to the corresponding address will be serviced from the main memory.

Abstract: Techniques are disclosed for implementing software breakpoints in a multiprocessor system having a number of processors each coupled to a main memory. In an illustrative embodiment, each of the processors has an instruction cache associated therewith. An instruction for which a breakpoint is to be inserted is retrieved from a corresponding instruction address in the main memory, and a breakpoint code is inserted at the instruction address in main memory. After the breakpoint code is executed by a given one of the processors, the retrieved instruction is stored in the corresponding instruction cache for that processor, and a use-once indicator is set.

Abstract: An integrated circuit or other type of digital system including multiple processors is tested using a control mechanism which dynamically defines a group of processors subject to common control. The control mechanism receives one or more commands for each of the processors in the group, and delays issuance of one or more of the commands for the group until a designated group scan command is received for each of the processors in the group. The control mechanism may be in the form of a software-implemented chain manager which provides the above-noted group definition, command receipt and issuance delay operations, and subsequently delivers one or more of the test commands as a single serial bit stream to an IEEE 1149.1 hardware scan chain associated with the processors. The control mechanism can provide synchronous control for a group of homogeneous processors of the digital system, or pseudo-synchronous control for a group of heterogeneous processors of the digital system.

Abstract: Techniques are disclosed for implementing software breakpoints in a processor system having at least one processor coupled to a main memory. In an illustrative embodiment, each of the processors in a shared-memory multiprocessor system has an instruction cache associated therewith. A breakpoint code is inserted at a particular location in the instruction cache of at least a given one of the processors, and a control indicator associated with the particular location is set to a first state which allows the breakpoint code to be returned to the given processor from the instruction cache in response to a first fetch request directed to a corresponding address.

Abstract: Techniques are disclosed for implementing software breakpoints in a multiprocessor system having a number of processors each coupled to a main memory. In an illustrative embodiment, each of the processors has an instruction cache associated therewith. An instruction for which a breakpoint is to be inserted is retrieved from a corresponding instruction address in the main memory, and a breakpoint code, e.g., a debug opcode, is inserted at the instruction address in main memory. After the breakpoint code is executed by a given one of the processors, the retrieved instruction is stored in the corresponding instruction cache for that processor, and a use-once indicator, associated with the instruction as stored in the corresponding instruction cache for that processor, is set.

Abstract: There is disclosed an integrated circuit including a digital processor having EEPROM and a control register. The digital processor is capable of receiving data to be programmed into the EEPROM and is capable of programming the data into the EEPROM. The digital processor includes a control register for receiving bits to control a write line and an erase line. The digital processor also includes a processor core coupled to the control register by a data bus, the digital processor is coupled to the EEPROM by a ROM address bus and a RAM data bus. The EEPROM memory location identified by the ROM address bus is programmed to retain data latched onto the RAM data bus. This is achieved by the digital processor writing control bits to the control register to enable the write line for a write operation of sufficient duration to assure that the data on the RAM data bus is retained in the EEPROM memory address that is enabled.