Abstract: A computer system is provided wherein a bus master generates a signal indicative of the type of cycle it plans to initiate when requesting bus ownership. Other bus masters may be configured to generate similar cycle-type signals. A bus arbiter samples each master's unique cycle type signal during the request phase, and further receives information regarding the status of various target resources. Based upon the cycle type signals from requesting masters and upon the target resource information, the bus arbiter determines whether a master is planning to access an unavailable target resource. A master that is planning to access an unavailable target resource will be denied access of the bus. Accordingly, other masters intending to initiate cycles to available target resources may be granted ownership of the bus. As a result, target termination retry cycles may be avoided, and bus bandwidth and overall system performance may be improved.

Abstract: A PCI bus master which determines the termination characteristics of one or more PCI targets coupled to the bus and uses this information to eliminate the wait states that are incurred during a bus cycle when a target device attempts to perform a data phase termination. According to the present invention, at initialization the bus master performs burst cycles on arbitrary address boundaries and stores the target's termination boundaries and cycle conditions. The bus master uses this information during burst transfers to initiate the data phase termination prior to the target, thus preempting the target from performing this termination. This operates to maintain the target's maximum burst capabilities while also eliminating the rearbitration wait states incurred when the bus master receives a termination from the target device. This also allows the bus master to chain together fast back-to-back PCI cycles while retaining bus ownership.

Abstract: A daughter card for mounting to an adapter card, wherein the daughter card includes adapter card connectors for mounting to the adapter card and also an edge connector for insertion directly into a computer slot so that the daughter card may also function as a stand-alone card. The daughter card is both mechanically and electrically compliant as an independent PCI add-in card and includes a PCI edge connector for insertion directly into a PCI slot. This provides additional modularity since the daughter card can be purchased and configured as a separate and independent PCI adapter card as well as for mating to a host adapter card to provide extra functionality to the host adapter card. In addition, since the daughter card can be directly inserted into the PCI bus, the daughter card provides greater component access and probing for testing. Further, the daughter card can be tested independently of the host adapter card during manufacturing functional test, thus providing more reliable testing.