Abstract: An apparatus comprises a memory array comprising access lines, digit lines, and memory cells. Each memory cell is coupled to an associated access line and an associated digit line and each memory cell comprises an access device, and a monocrystalline semiconductor material adjacent to the access device. A width of the monocrystalline semiconductor material is within a range of from about 8 nm to about 25 nm. Each memory cell comprises a metal silicide material over the monocrystalline semiconductor material, a metal contact material over the metal silicide material, and a storage node adjacent to the metal contact material. Methods of forming an apparatus and systems are also disclosed.

Abstract: A method of forming an apparatus comprises forming a crystalline semiconductor material comprising one or more of a monocrystalline material and a nanocrystalline material adjacent to active areas of memory cells, forming an amorphous material within portions of the crystalline semiconductor material, forming a metal material comprising one or more of chlorine atoms and nitrogen atoms over the amorphous material, converting a portion of the amorphous material and the metal material to form a metal silicide material adjacent to the crystalline semiconductor material, forming cell contacts over the metal silicide material, and forming a storage node adjacent to the cell contacts. Additional methods and apparatus are also disclosed.

Abstract: Bit lines having high electrical conductivity and low mutual capacitance and related apparatuses, computing systems, and methods are disclosed. An apparatus includes bit lines including copper, a low-k dielectric material between the bit lines, and air gaps between the bit lines. The low-k dielectric material mechanically supports the bit lines. A method of manufacturing a memory device includes forming a first electrically conductive material in bit line trenches of an electrically insulating material, removing portions of the electrically insulating material between the bit line trenches, conformally forming a low-k dielectric material on the first electrically conductive material and remaining portions of the electrically insulating material, and forming a subconformal dielectric material to form air gaps between the bit line trenches.

Abstract: An oxidation barrier for non-volatile memory with materials sensitive to temperature and/or cross contamination (e.g., chalcogenide materials) are described The barrier can be formed, for example, around the boundaries of a non-volatile memory tile (also known as a block or sub-array). For example, a non-volatile memory device can include an oxidation barrier on a side wall of a trench between adjacent memory tiles.

Abstract: An oxidation barrier for non-volatile memory with materials sensitive to temperature and/or cross contamination (e.g., chalcogenide materials) are described The barrier can be formed, for example, around the boundaries of a non-volatile memory tile (also known as a block or sub-array). For example, a non-volatile memory device can include an oxidation barrier on a side wall of a trench between adjacent memory tiles.

Abstract: An oxidation barrier for non-volatile memory with materials sensitive to temperature and/or cross contamination (e.g., chalcogenide materials) are described The barrier can be formed, for example, around the boundaries of a non-volatile memory tile (also known as a block or sub-array). For example, a non-volatile memory device can include an oxidation barrier on a side wall of a trench between adjacent memory tiles.