Abstract: A backside metal ground plane with improved metal adhesion and methods of manufacture are disclosed herein. The method includes forming at least one through silicon via (TSV) in a substrate. The method further includes forming an oxide layer on a backside of the substrate. The method further includes forming a metalized ground plane on the oxide layer and in electrical contact with an exposed portion of the at least one TSV.

Abstract: A backside metal ground plane with improved metal adhesion and methods of manufacture are disclosed herein. The method includes forming at least one through silicon via (TSV) in a substrate. The method further includes forming an oxide layer on a backside of the substrate. The method further includes forming a metalized ground plane on the oxide layer and in electrical contact with an exposed portion of the at least one TSV.

Abstract: In one embodiment, the invention is a method and apparatus for sub-pellicle defect reduction on photomasks. One embodiment of a photomask for use in photolithography includes a substrate on which a pattern is formed, the substrate having a frontside and an opposite backside, and a protective coating formed on at least one of the frontside and the backside, the protective coating comprising silicon-based compound.

Abstract: A method of fabricating a gate dielectric layer. The method includes: providing a substrate; forming a silicon dioxide layer on a top surface of the substrate; performing a plasma nitridation in a reducing atmosphere to convert the silicon dioxide layer into a silicon oxynitride layer. The dielectric layer so formed may be used in the fabrication of MOSFETs.

Abstract: In one embodiment, the invention is a method and apparatus for sub-pellicle defect reduction on photomasks. One embodiment of a photomask for use in photolithography includes a substrate on which a pattern is formed, the substrate having a frontside and an opposite backside, and a protective coating formed on at least one of the frontside and the backside, the protective coating comprising silicon-based compound.

Abstract: In one embodiment, the invention is a method and apparatus for sub-pellicle defect reduction on photomasks. One embodiment of a photomask for use in photolithography includes a substrate on which a pattern is formed, the substrate having a frontside and an opposite backside, and a protective coating formed on at least one of the frontside and the backside, the protective coating comprising silicon-based compound.

Abstract: A method of fabricating a semiconductor structure. The method includes forming a first feature of a first active device and a second feature of a second active device, introducing a first amount of nitrogen into the first feature of the first active device, and introducing a second amount of nitrogen into the second feature of the second active device, the second amount of nitrogen being different from the first amount of nitrogen.

Abstract: A method of fabricating a semiconductor structure. The method includes forming a first feature of a first active device and a second feature of a second active device, introducing a first amount of nitrogen into the first feature of the first active device, and introducing a second amount of nitrogen into the second feature of the second active device, the second amount of nitrogen being different from the first amount of nitrogen.

Abstract: In one embodiment, the invention is a method and apparatus for sub-pellicle defect reduction on photomasks. One embodiment of a photomask for use in photolithography includes a substrate on which a pattern is formed, the substrate having a frontside and an opposite backside, and a protective coating formed on at least one of the frontside and the backside, the protective coating comprising silicon-based compound.

Abstract: A bilayer dielectric structure for substantially reducing or eliminating metal contaminants formed during subsequent polysilicon deposition is provided. The bilayer dielectric structure includes an upper surface region that is rich in chlorine located atop a bottom surface region. The upper surface region that is rich in chlorine removes metal contaminates that are present atop the structure during subsequent formation of a polysilicon layer. A method of forming the bilayer structure is also provided.

Abstract: A method of fabricating a gate dielectric layer, including: providing a substrate; forming a silicon dioxide layer on a top surface of the substrate; performing a plasma nitridation in a reducing atmosphere to convert the silicon dioxide layer into a silicon oxynitride layer. The dielectric layer so formed may be used in the fabrication of MOSFETs.

Abstract: A semiconductor structure includes thin gate dielectrics that have been selectively nitrogen enriched. The amount of nitrogen introduced is sufficient to reduce or prevent gate leakage and dopant penetration, without appreciably degrading device performance. A lower concentration of nitrogen is introduced into pFET gate dielectrics than into nFET gate dielectrics. Nitridation may be accomplished selectively by various techniques, including rapid thermal nitridation (RTN), furnace nitridation, remote plasma nitridation (RPN), decoupled plasma nitridation (DPN), well implantation and/or polysilicon implantation.

Abstract: Methods such as Remote Plasma Nitridation (RPN) are used to introduce nitrogen into a gate dielectric layer. However, these methods yield nitrided layers where the layers are not uniform, both in cross-sectional profile and in nitrogen profile. Subjecting the nitrided layer to an additional NO anneal process increases the uniformity of the nitrided layer.

Abstract: A bilayer dielectric structure for substantially reducing or eliminating metal contaminants formed during subsequent polysilicon deposition is provided. The bilayer dielectric structure includes an upper surface region that is rich in chlorine located atop a bottom surface region. The upper surface region that is rich in chlorine removes metal contaminates that are present atop the structure during subsequent formation of a polysilicon layer. A method of forming the bilayer structure is also provided.

Abstract: A bilayer dielectric structure for substantially reducing or eliminating metal contaminants formed during subsequent polysilicon deposition is provided. The bilayer dielectric structure includes an upper surface region that is rich in chlorine located atop a bottom surface region. The upper surface region that is rich in chlorine removes metal contaminates that are present atop the structure during subsequent formation of a polysilicon layer. A method of forming the bilayer structure is also provided.

Abstract: A method of fabricating a gate dielectric layer. The method comprises: providing a substrate; forming a silicon dioxide layer on a top surface of the substrate; exposing the silicon dioxide layer to a plasma nitridation to convert the silicon dioxide layer into a silicon oxynitride layer; and performing a spiked rapid thermal anneal of the silicon oxynitride layer.

Abstract: Methods such as Remote Plasma Nitridation (RPN) are used to introduce nitrogen into a gate dielectric layer. However, these methods yield nitrided layers where the layers are not uniform, both in cross-sectional profile and in nitrogen profile. Subjecting the nitrided layer to an additional NO anneal process increases the uniformity of the nitrided layer.

Abstract: Methods such as Remote Plasma Nitridation (RPN) are used to introduce nitrogen into a gate dielectric layer. However, these methods yield nitrided layers where the layers are not uniform, both in cross-sectional profile and in nitrogen profile. Subjecting the nitrided layer to an additional NO anneal process increases the uniformity of the nitrided layer.

Abstract: A method of fabricating a gate dielectric layer. The method comprises: providing a substrate; forming a silicon dioxide layer on a top surface of the substrate; exposing the silicon dioxide layer to a plasma nitridation to convert the silicon dioxide layer into a silicon oxynitride layer; and performing a spiked rapid thermal anneal of the silicon oxynitride layer.